公开(公告)号：US06441646B1

公开(公告)日：2002-08-27

申请号：US09682903

申请日：2001-10-31

申请人： George M. Braceras ,  Patrick R. Hansen

发明人： George M. Braceras ,  Patrick R. Hansen

IPC分类号： H03K19091

CPC分类号： H03K19/0963

摘要： A structure and method for reducing bipolar current in of a SOI circuit by alternating precharge low and precharge high methodologies comprises a reset signal source coupled to an inverter and a primary node, further coupled to a first and second PFET device; a clock signal source; coupled to a first NFET device and a third PFET device; a first input signal source coupled to a second NFET device and a fourth PFET device; a first NFET stack node coupled to the third PFET device, the first NFET device, the primary node, and the second NFET device; a second input signal source coupled to a third NFET device; a fifth PFET device coupled to the fourth PFET device; a power supply voltage source coupled to the fifth PFET device; and a second NFET node coupled to the fourth PFET device, the second NFET device, and the third NFET device.

摘要翻译： 通过交替预充电低和预充电高方法来减少SOI电路中的双极电流的结构和方法包括耦合到反相器和主节点的复位信号源，还耦合到第一和第二PFET器件; 时钟信号源; 耦合到第一NFET器件和第三PFET器件; 耦合到第二NFET器件和第四PFET器件的第一输入信号源; 耦合到第三PFET器件，第一NFET器件，主节点和第二NFET器件的第一NFET堆叠节点; 耦合到第三NFET器件的第二输入信号源; 耦合到第四PFET器件的第五PFET器件; 耦合到所述第五PFET器件的电源电压源; 以及耦合到第四PFET器件，第二NFET器件和第三NFET器件的第二NFET节点。