公开(公告)号：US06226044B1

公开(公告)日：2001-05-01

申请号：US08351201

申请日：1994-11-30

申请人： Curtis M. Webb

发明人： Curtis M. Webb

IPC分类号： H04N510

CPC分类号： H04N5/33 ,  H04N5/10

摘要： A field synchronization system of a field detect circuit adaptable for use with non-standard output digital data of forward looking infrared (FLIR) sensors. Timing signals and digital data from a FLIR sensor are utilized and there is outputted a vertical and horizontal signal output. A bypass circuit allows for the optional bypass of frame grabber generated field index circuitry so that an external field index signal is utilized.

摘要翻译： 适用于前瞻性红外（FLIR）传感器的非标准输出数字数据的场检测电路的现场同步系统。 利用来自FLIR传感器的定时信号和数字数据，输出垂直和水平信号输出。 旁路电路允许帧捕获器产生的场索引电路的可选旁路，从而利用外部场索引信号。

公开(公告)号：US06271889B1

公开(公告)日：2001-08-07

申请号：US09262589

申请日：1999-03-04

申请人： Christian Willibald Böhm ,  Michael Patrick Daly ,  Kieran Heffernan

发明人： Christian Willibald Böhm ,  Michael Patrick Daly ,  Kieran Heffernan

IPC分类号： H04N510

CPC分类号： H04N5/10

摘要： A synchronization pulse detector for detecting a synchronization pulse within an input signal. The input signal has “level” portions (i.e., substantially non-time varying portions) and “transition” portions (i.e., substantially time varying portions). The pulse detector includes a pulse shape detector for determining each time the input signal has a sequence of a first “level” portion, followed by a first “transition” portion, followed by a second “level” portion, followed by a second “transition” portion followed by a third “level” portion, one of the first and second “transition” portions being positive and the other one of the first and second “transition” portions being negative. Each time such sequence is determined a pulse_shape detected pulse is produced. An evaluator is provided to reject invalid pulse_shape detected pulses. In one embodiment, the input signal is a video signal and the evaluator includes a time window for determining whether such shape_detected pulses are produced at a predetermined rate expected for the series of synchronization pulses. The evaluator includes a voltage window responsive to the produced shape_detected pulses and their associated values of the second “level” portions for determining whether one of such produced second “level” portions is substantially the same as or lower but not higher than the lowest DC value recorded during the time-equivalent of one line of video. The evaluator may include both the time window and the voltage window. The voltage window is mainly used to acquire an initial lock to an unknown and not yet clamped video signal.

摘要翻译： 一种用于检测输入信号内的同步脉冲的同步脉冲检测器。 输入信号具有“电平”部分（即，基本上非时变部分）和“转变”部分（即基本上时变部分）。 脉冲检测器包括脉冲形状检测器，用于每次输入信号具有第一“电平”部分的序列，随后是第一“转换”部分，随后是第二“电平”部分，随后进行第二“转换” “部分之后是第三”级“部分，第一和第二”转换“部分之一是正的，第一和第二”转换“部分中的另一个是负的。 每次确定这样的序列时，产生脉冲形状检测脉冲。 提供评估器来拒绝无效的pulse_shape检测脉冲。 在一个实施例中，输入信号是视频信号，并且评估器包括一个时间窗口，用于确定是否以针对该系列同步脉冲预期的预定速率产生这种形状检测脉冲。 评估器包括响应于产生的形状检测脉冲及其相关值的第二“电平”部分的电压窗口，用于确定这样产生的第二“电平”部分中的一个是基本上相同还是不高于最低DC值 在相当于一行视频的时间内记录。 评估器可以包括时间窗和电压窗。 电压窗口主要用于获取未知且尚未钳位的视频信号的初始锁定。

公开(公告)号：US06369856B1

公开(公告)日：2002-04-09

申请号：US09108032

申请日：1998-06-30

申请人： Tae Bo Jeong

发明人： Tae Bo Jeong

IPC分类号： H04N510

CPC分类号： H04N5/10

摘要： A synchronous signal detection circuit which detect a vertical synchronous signal and a horizontal synchronous signal from composite synchronous signal, including: a reset generation means for receiving an external composite synchronous signal and an external main clock signal to generate a reset signal at falling edge of the composite synchronous signal; a counter means being reset by the reset signal received from the reset generation means and for counting the main clock signal to generate first through fourth output signals; a vertical synchronous signal detection means for receiving the second output signal of the counter means and the composite synchronous signal to detect the vertical synchronous signal of the composite synchronous signal and generating the vertical synchronous signal; and a horizontal synchronous signal detection means for receiving the third and the fourth output signals of the counter means and the reset signal of the reset generation means to detect the horizontal synchronous signal of composite synchronous signal having a period of 1 horizontal scanning interval (1H).

摘要翻译： 一种从复合同步信号检测垂直同步信号和水平同步信号的同步信号检测电路，包括：复位产生装置，用于接收外部复合同步信号和外部主时钟信号，以在下行沿产生复位信号 复合同步信号; 计数器装置由从复位产生装置接收到的复位信号复位，并用于对主时钟信号进行计数以产生第一至第四输出信号; 垂直同步信号检测装置，用于接收计数装置的第二输出信号和复合同步信号，以检测复合同步信号的垂直同步信号并产生垂直同步信号; 以及水平同步信号检测装置，用于接收计数器装置的第三和第四输出信号和复位产生装置的复位信号，以检测具有1个水平扫描间隔（1H）的周期的复合同步信号的水平同步信号， 。

公开(公告)号：US06222590B1

公开(公告)日：2001-04-24

申请号：US09141719

申请日：1998-08-27

申请人： Yuji Makino

发明人： Yuji Makino

IPC分类号： H04N510

CPC分类号： H04N5/126 ,  G09G5/12

摘要： In a phase-locked loop circuit, a vertical synchronous separation circuit separates a vertical sync signal from a composite synchronizing signal to detect part of a vertical synchronizing period. A mask circuit masks the composite synchronizing signal during a predetermined period. A selector selects a reference signal or the composite synchronizing signal in accordance with the detection output from the vertical synchronous separation circuit. A phase comparator detects a phase difference between the output from the selector and the reference signal. A voltage-controlled oscillator changes an oscillation frequency upon receiving the output from the phase comparator through a low-pass filter. A counter counts the oscillation output from the voltage-controlled oscillator. A decoder circuit decodes the output from the counter to generate the reference signal, supplies it to the selector and the phase comparator, and resets the counter at a predetermined period. A mask pulse decoder generates a mask pulse to control a mask period of the mask circuit. The composite synchronizing signal is replaced with the reference signal in accordance with the detection output from the vertical synchronous separation circuit and supplied to an input of the phase comparator.

摘要翻译： 在锁相环电路中，垂直同步分离电路将垂直同步信号与复合同步信号分离，以检测垂直同步周期的一部分。 掩模电路在预定时段期间掩蔽复合同步信号。 选择器根据来自垂直同步分离电路的检测输出来选择参考信号或复合同步信号。 相位比较器检测来自选择器的输出和参考信号之间的相位差。 压控振荡器通过低通滤波器从相位比较器接收到输出时改变振荡频率。 计数器对来自压控振荡器的振荡输出进行计数。 解码器电路对来自计数器的输出进行解码以产生参考信号，将其提供给选择器和相位比较器，并以预定周期复位计数器。 掩模脉冲解码器产生掩模脉冲以控制掩模电路的屏蔽周期。 根据来自垂直同步分离电路的检测输出，将复合同步信号替换为参考信号，并提供给相位比较器的输入端。

公开(公告)号：US06563545B1

公开(公告)日：2003-05-13

申请号：US09647323

申请日：2000-09-28

申请人： Junji Masumoto

发明人： Junji Masumoto

IPC分类号： H04N510

CPC分类号： H04N5/08 ,  H04N5/06 ,  H04N5/10

摘要： With the present invention, a synchronous processor circuit can be implemented with a simplified circuit by improving a display's synchronization stability, and by setting a pulse width of a vertical synchronizing signal to be integral multiple of the horizontal synchronizing signal.

摘要翻译： 利用本发明，可以通过改善显示器的同步稳定性，并且通过将垂直同步信号的脉冲宽度设置为水平同步信号的整数倍来实现具有简化电路的同步处理器电路。

公开(公告)号：US06456332B1

公开(公告)日：2002-09-24

申请号：US09114158

申请日：1998-07-13

申请人： Moon-Jong Song

发明人： Moon-Jong Song

IPC分类号： H04N510

CPC分类号： H04N9/641 ,  G09G5/18 ,  G09G2340/125 ,  H04N5/08

摘要： A device which generates horizontal and vertical sync signals of a composite signal to create a soft picture on a display monitor by preventing a free running effect of a composite signal which is caused by a mode conversion between recorded and unrecorded areas of the picture when a composite signal generated from an alternative source such as a VCR instead of an external input signal is applied to the display monitor. The device includes a microcomputer for generating a sync select signal based on a display mode, and a composite signal analyzing and horizontal/vertical oscillating circuit for generating horizontal and vertical oscillating signals based on a luminance signal separated from a composite signal input. A horizontal sync signal generator processes the horizontal oscillating signal, to generate a composite horizontal sync signal. A vertical sync signal generator processes the vertical oscillating signal, to generate a composite vertical sync signal. A sync signal switching circuit selectively outputs one pair among the composite horizontal and vertical sync signals respectively generated from the horizontal and vertical sync signal generator and horizontal and vertical sync signals transmitted from a host computer in response to the select signal generated by the microcomputer.

摘要翻译： 一种产生复合信号的水平和垂直同步信号以在显示监视器上产生软图像的装置，其通过防止由复合信号在图像的记录区域和未记录区域之间的模式转换引起的自由运行效应 从显示监视器等将诸如VCR等替代的信号源而不是外部的输入信号生成的信号应用于显示监视器。 该装置包括用于基于显示模式产生同步选择信号的微型计算机，以及用于基于从复合信号输入分离的亮度信号产生水平和垂直振荡信号的复合信号分析和水平/垂直振荡电路。 水平同步信号发生器处理水平振荡信号，以产生复合水平同步信号。 垂直同步信号发生器处理垂直振荡信号，以产生复合垂直同步信号。 同步信号切换电路响应于微计算机产生的选择信号，选择性地输出从水平和垂直同步信号发生器分别产生的复合水平和垂直同步信号中的一对以及从主计算机发送的水平和垂直同步信号。

公开(公告)号：US06788351B2

公开(公告)日：2004-09-07

申请号：US09935362

申请日：2001-08-22

申请人： Jae-hoon Lee

发明人： Jae-hoon Lee

IPC分类号： H04N510

CPC分类号： G09G1/002 ,  H04N3/24 ,  H04N5/148 ,  H04N5/44504 ,  H04N5/68

摘要： A fly-back pulse width adjustment circuit and a method for adjusting the width of a fly-back pulse which are applied to a video signal processing unit realized as one chip are provided. The fly-back pulse width adjustment circuit is built into a video signal processing unit including a video amplifier, an on screen display unit, and a horizontal/vertical synchronous signal processing unit within the video signal processing unit realized as one chip. Moreover the fly-back pulse width adjustment circuit includes a pulse shaping unit which shapes the fly-back pulse received from the outside via an input terminal and then applies the shaped fly-back pulse to the horizontal/vertical synchronous signal processing unit, and a pulse-width adjustment unit which adjusts the width of the shaped fly-back pulse in response to a predetermined control signal, generates the horizontal blank signal having a different occurrence time from the result of the adjustment in response to a selection signal, and applies the horizontal blank signal to the video amplifier and the on screen display unit. The fly-back pulse width adjustment circuit which is provided as external components of a chip is designed to have a simple structure, and consequently it is possible to build the fly-back pulse width adjustment circuit into a video signal processing unit realized as one chip. Moreover, the width of a fly-back pulse can be adjusted by control of a microcontroller or a microcomputer, thereby applying the fly-back pulse width adjustment circuit to various monitors. In addition, the fly-back pulse width adjustment circuit can input the fly-back pulse via one terminal without an external circuit. Therefore it is easy to manufacture a printed circuit substrate with use of the fly-back pulse width adjustment circuit.

摘要翻译： 提供了一种回扫脉冲宽度调整电路和用于调整反向脉冲宽度的方法，该反射脉冲施加到实现为一个芯片的视频信号处理单元。 回扫脉冲宽度调整电路内置在视频信号处理单元中，视频信号处理单元包括视频放大器，屏幕显示单元以及作为一个芯片实现的视频信号处理单元内的水平/垂直同步信号处理单元。 此外，回扫脉冲宽度调整电路包括：脉冲整形单元，其经由输入端子对从外部接收的反激脉冲进行整形，然后将成形的反激脉冲施加到水平/垂直同步信号处理单元， 脉冲宽度调整单元，其响应于预定的控制信号调整成形的反激脉冲的宽度，响应于选择信号产生与调整结果不同的出现时间的水平空白信号， 水平空白信号到视频放大器和屏幕显示单元。 作为芯片的外部部件设置的回扫脉冲宽度调整电路被设计为具有简单的结构，因此可以将回扫脉冲宽度调整电路构建成实现为一个芯片的视频信号处理单元 。 此外，可以通过微控制器或微型计算机的控制来调整回扫脉冲的宽度，从而将回扫脉冲宽度调节电路应用于各种监视器。 此外，回扫脉冲宽度调整电路可以经由一个端子输入反激脉冲，而不需要外部电路。 因此，使用回扫脉冲宽度调节电路容易制造印刷电路基板。

公开(公告)号：US06704056B2

公开(公告)日：2004-03-09

申请号：US09861587

申请日：2001-05-22

申请人： Toshiaki Kitahara ,  Hideyo Uwabata ,  Yutaka Nishikawa ,  Chikara Gotanda

发明人： Toshiaki Kitahara ,  Hideyo Uwabata ,  Yutaka Nishikawa ,  Chikara Gotanda

IPC分类号： H04N510

CPC分类号： H04N5/63 ,  H04N3/16

摘要： A video signal conversion part of a horizontal deflection circuit deletes a prescribed number of horizontal scanning lines from a vertical blanking interval of an input video signal and assigns a time corresponding to the deleted horizontal scanning lines to horizontal blanking intervals of the remaining horizontal scanning lines thereby extending the horizontal blanking interval of each horizontal scanning line and outputting a video signal. A synchronizing signal separation circuit extracts a horizontal synchronizing signal and a vertical synchronizing signal from the video signal output from the video signal conversion part. An output part of the horizontal deflection circuit supplies a sawtooth horizontal deflection current to a horizontal deflection yoke in synchronization with the horizontal synchronizing signal output from the synchronizing signal separation circuit.

摘要翻译： 水平偏转电路的视频信号转换部分从输入视频信号的垂直消隐间隔中删除规定数量的水平扫描线，并将与删除的水平扫描线对应的时间分配给其余水平扫描线的水平消隐间隔，由此 延长每条水平扫描线的水平消隐间隔并输出视频信号。 同步信号分离电路从视频信号转换部分输出的视频信号中提取水平同步信号和垂直同步信号。 水平偏转电路的输出部分与从同步信号分离电路输出的水平同步信号同步地向水平偏转线圈提供锯齿水平偏转电流。