公开(公告)号：US07176979B2

公开(公告)日：2007-02-13

申请号：US09905786

申请日：2001-07-13

申请人： Christian Willibald Böhm ,  Michael Patrick Daly ,  Kieran Heffernan

发明人： Christian Willibald Böhm ,  Michael Patrick Daly ,  Kieran Heffernan

IPC分类号： H04N5/10

CPC分类号： H04N5/10

摘要： A synchronization pulse detector includes an absolute value independent shape detector for processing samples of an input signal having a synchronization pulse and a plurality of non-synchronization pulses to determine whether such samples have a predetermined sequence. The predetermined sequence includes a first and second absolute value independent time-varying portions and a first and second absolute value independent non-time varying portions. One of the first and second absolute value independent time-varying portions having a positive slope and the other one of the first and second absolute value independent time-varying portions having a negative slope.

摘要翻译： 同步脉冲检测器包括用于处理具有同步脉冲和多个非同步脉冲的输入信号的样本的绝对值独立形状检测器，以确定这样的样本是否具有预定的序列。 预定序列包​​括第一和第二绝对值独立时变部分和第一和第二绝对值独立的非时变部分。 具有正斜率的第一和第二绝对值独立时变部分之一，第一和第二绝对值独立时变部分中的另一个具有负斜率。

公开(公告)号：US06271889B1

公开(公告)日：2001-08-07

申请号：US09262589

申请日：1999-03-04

申请人： Christian Willibald Böhm ,  Michael Patrick Daly ,  Kieran Heffernan

发明人： Christian Willibald Böhm ,  Michael Patrick Daly ,  Kieran Heffernan

IPC分类号： H04N510

CPC分类号： H04N5/10

摘要： A synchronization pulse detector for detecting a synchronization pulse within an input signal. The input signal has “level” portions (i.e., substantially non-time varying portions) and “transition” portions (i.e., substantially time varying portions). The pulse detector includes a pulse shape detector for determining each time the input signal has a sequence of a first “level” portion, followed by a first “transition” portion, followed by a second “level” portion, followed by a second “transition” portion followed by a third “level” portion, one of the first and second “transition” portions being positive and the other one of the first and second “transition” portions being negative. Each time such sequence is determined a pulse_shape detected pulse is produced. An evaluator is provided to reject invalid pulse_shape detected pulses. In one embodiment, the input signal is a video signal and the evaluator includes a time window for determining whether such shape_detected pulses are produced at a predetermined rate expected for the series of synchronization pulses. The evaluator includes a voltage window responsive to the produced shape_detected pulses and their associated values of the second “level” portions for determining whether one of such produced second “level” portions is substantially the same as or lower but not higher than the lowest DC value recorded during the time-equivalent of one line of video. The evaluator may include both the time window and the voltage window. The voltage window is mainly used to acquire an initial lock to an unknown and not yet clamped video signal.

摘要翻译： 一种用于检测输入信号内的同步脉冲的同步脉冲检测器。 输入信号具有“电平”部分（即，基本上非时变部分）和“转变”部分（即基本上时变部分）。 脉冲检测器包括脉冲形状检测器，用于每次输入信号具有第一“电平”部分的序列，随后是第一“转换”部分，随后是第二“电平”部分，随后进行第二“转换” “部分之后是第三”级“部分，第一和第二”转换“部分之一是正的，第一和第二”转换“部分中的另一个是负的。 每次确定这样的序列时，产生脉冲形状检测脉冲。 提供评估器来拒绝无效的pulse_shape检测脉冲。 在一个实施例中，输入信号是视频信号，并且评估器包括一个时间窗口，用于确定是否以针对该系列同步脉冲预期的预定速率产生这种形状检测脉冲。 评估器包括响应于产生的形状检测脉冲及其相关值的第二“电平”部分的电压窗口，用于确定这样产生的第二“电平”部分中的一个是基本上相同还是不高于最低DC值 在相当于一行视频的时间内记录。 评估器可以包括时间窗和电压窗。 电压窗口主要用于获取未知且尚未钳位的视频信号的初始锁定。

公开(公告)号：US20070019770A1

公开(公告)日：2007-01-25

申请号：US11453684

申请日：2006-06-15

申请人： Shaun Bradley ,  Kieran Heffernan ,  Tomas Tansley ,  Yang Ling

发明人： Shaun Bradley ,  Kieran Heffernan ,  Tomas Tansley ,  Yang Ling

IPC分类号： H04L7/02

CPC分类号： H04L7/0004 ,  G06F1/04 ,  H03L1/00 ,  H03L7/00

摘要： A microprocessor programmable clock calibration device compares, in response to a calibration command from a programmable processor, turns on a normally off reference oscillator clock, compares the frequency of the reference oscillator clock with the frequency of a calibratable oscillator clock, turns off the reference oscillator clock and adjusts, in response to a difference in those frequencies, the frequency of the calibratable oscillator clock towards that of the reference oscillator clock.

摘要翻译： 微处理器可编程时钟校准装置响应来自可编程处理器的校准命令来比较正常关断参考振荡器时钟，将参考振荡器时钟的频率与可校准振荡器时钟的频率进行比较，将参考振荡器 响应于这些频率的差异，可调整校准振荡器时钟频率与参考振荡器时钟的频率。

公开(公告)号：US07890787B2

公开(公告)日：2011-02-15

申请号：US11453684

申请日：2006-06-15

申请人： Shaun Bradley ,  Kieran Heffernan ,  Tomas Tansley ,  Yang Ling

发明人： Shaun Bradley ,  Kieran Heffernan ,  Tomas Tansley ,  Yang Ling

IPC分类号： G06F1/12

CPC分类号： H04L7/0004 ,  G06F1/04 ,  H03L1/00 ,  H03L7/00

摘要： A microprocessor programmable clock calibration device compares, in response to a calibration command from a programmable processor, turns on a normally off reference oscillator clock, compares the frequency of the reference oscillator clock with the frequency of a calibratable oscillator clock, turns off the reference oscillator clock and adjusts, in response to a difference in those frequencies, the frequency of the calibratable oscillator clock towards that of the reference oscillator clock.

摘要翻译： 微处理器可编程时钟校准装置响应来自可编程处理器的校准命令来比较正常关断参考振荡器时钟，将参考振荡器时钟的频率与可校准振荡器时钟的频率进行比较，将参考振荡器 响应于这些频率的差异，可调整校准振荡器时钟频率与参考振荡器时钟的频率。

公开(公告)号：US06236087B1

公开(公告)日：2001-05-22

申请号：US09184924

申请日：1998-11-02

申请人： Michael P. Daly ,  Denis Ellis ,  Keith A. Moloney ,  Liam J. White ,  Brian A. Moane ,  Kieran Heffernan ,  Denis Joseph Doyle ,  Michael G. Tuthill ,  David John Clarke

发明人： Michael P. Daly ,  Denis Ellis ,  Keith A. Moloney ,  Liam J. White ,  Brian A. Moane ,  Kieran Heffernan ,  Denis Joseph Doyle ,  Michael G. Tuthill ,  David John Clarke

IPC分类号： H01L2362

CPC分类号： H01L27/0262 ,  H01L29/0692 ,  H01L29/747 ,  H01L29/87

摘要： An input protection device is provided for protecting a circuit structure which is coupled to a first node, the device comprising a first lightly-doped region of P-type material with a lightly doped well of N-type material formed in it. Two regions of heavily doped N-type and P-type material, which are electrically connected to the first node, are formed in the well of N-type material. A third heavily doped region of N type material is formed in the first lightly-doped region of P-type material and is electrically connected to a reference node. In a first aspect of this invention, the third heavily doped region of N type material is formed in a second well of N-type material, which in turn is formed in the first lightly-doped region of P-type material. In this first aspect of the invention a further region of heavily doped P-type material is formed in the second well of N-type material, this further region of heavily doped P-type material being electrically connected to the reference node. In a second aspect to the invention, a further region of heavily doped P-type material is formed in the first lightly-doped region of P-type material. In a third aspect to the invention, the third heavily doped region of N type material is formed in a second well of N-type material, which in turn is formed in the first lightly-doped region of P-type material. In this third aspect of the invention a further region of heavily doped P-type material is formed in the second well of N-type material, this further region of heavily doped P-type material being electrically connected to the reference node, with a further region of heavily doped P-type material formed in the first lightly-doped region of P-type material. Accordingly, an input protection device for protecting pins of an integrated circuit is described having both bipolar and unipolar characteristics. The input protection device may be constructed as a discrete device or as part of an integrated circuit and provides for breakdown voltages in excess of a supply voltage to an integrated circuit. The characteristics, in particular the breakdown voltage, of the input protection device are alterable by adjusting its layout, in contrast to a known method of altering such characteristics by altering doping levels.

公开(公告)号：US06411330B1

公开(公告)日：2002-06-25

申请号：US09095451

申请日：1998-06-10

申请人： John Patrick Purcell ,  Vincent James Troy ,  Kieran Heffernan

发明人： John Patrick Purcell ,  Vincent James Troy ,  Kieran Heffernan

IPC分类号： H04N5225

CPC分类号： H04N5/20 ,  H04N5/44 ,  H04N5/775

摘要： A detector circuit (1) for detecting the presence or absence of a television (2) on an output (3) of a video DAC (4) comprises a comparator (11) for comparing a voltage developed by the video signal on a control resistor R2 with a reference voltage of 0.5 volts. The resistor R2 is of 75 ohms and matches the internal impedance R1 of 75 ohms of the television (2). A latch (12) latches the output from the comparator (11) onto an output pin Q when the voltage developed across the control resistor R2 is developed by an equalisation pulse of the vertical blanking interval of the video signal. In the presence of a television (2) the voltage developed across the control resistor R2 is 0.35 volts, which pulls the output of the comparator (11) low, while in the absence of a television (2) the voltage developed across the control resistor R2 is 0.7 volts which pulls the output of the comparator (11) high. A control logic control circuit (21) reads the output pin Q of the latch (12) for powering up or powering down the video DAC (4) as appropriate.

摘要翻译： 一种用于检测在视频DAC（4）的输出（3）上是否存在电视（2）的检测器电路（1）包括比较器（11），用于将由视频信号产生的电压与控制电阻 R2的参考电压为0.5伏。 电阻R2为75欧姆，与电视（2）的75欧姆的内部阻抗R1相匹配。 当跨越控制电阻R2产生的电压由视频信号的垂直消隐间隔的均衡脉冲展开时，锁存器（12）将比较器（11）的输出锁存到输出引脚Q上。 在电视机（2）的存在下，跨越控制电阻器R2的电压为0.35伏特，其将比较器（11）的输出拉低，而不存在电视（2）跨越控制电阻器的电压 R2是0.7伏特，其将比较器（11）的输出拉高。 控制逻辑控制电路（21）适当地读取锁存器（12）的输出引脚Q，用于为视频DAC（4）供电或掉电。