公开(公告)号：WO2021119411A1

公开(公告)日：2021-06-17

申请号：PCT/US2020/064482

申请日：2020-12-11

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： RAASCH, Steven ,  KEGEL, Andrew G.

IPC: G06F13/16 ,  G06F3/06 ,  G06F12/1009

Abstract: A processing system includes a primary processor and a co-processor. The primary processor is couplable to a memory subsystem having at least one memory and operating to execute system software employing memory address translations based on one or more page tables stored in the memory subsystem. The co-processor is likewise couplable to the memory subsystem and operates to perform iterations of a page table walk through one or more page tables maintained for the memory subsystem and to perform one or more page management operations on behalf of the system software based the iterations of the page table walk. The page management operations performed by the co-processor include analytic data aggregation, free list management and page allocation, page migration management, page table error detection, and the like.

公开(公告)号：WO2019027554A1

公开(公告)日：2019-02-07

申请号：PCT/US2018/035377

申请日：2018-05-31

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： KEGEL, Andrew G. ,  ROBERTS, David A.

IPC: G06F9/50

Abstract: Systems, apparatuses, and methods for sharing an field programmable gate array compute engine are disclosed. A system includes one or more processors and one or more FPGAs. The system receives a request, generated by a first user process, to allocate a portion of processing resources on a first FPGA. The system maps the portion of processing resources of the first FPGA into an address space of the first user process. The system prevents other user processes from accessing the portion of processing resources of the first FPGA. Later, the system detects a release of the portion of the processing resources on the first FPGA by the first user process. Then, the system receives a second request to allocate the first FPGA from a second user process. In response to the second request, the system maps the first FPGA into an address space of the second user process.

公开(公告)号：WO2014055264A1

公开(公告)日：2014-04-10

申请号：PCT/US2013/060826

申请日：2013-09-20

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： PAPADOPOULOU, Misel-Myrto ,  HSU, Lisa R. ,  KEGEL, Andrew G. ,  NUWAN, Jayasena S. ,  BECKMANN, Bradford M. ,  REINHARDT, Steven K.

IPC: G06F12/10 ,  G06F9/48

CPC classification number: G06F12/1027 ,  G06F9/4856 ,  G06F2212/654 ,  Y02D10/13 ,  Y02D10/24 ,  Y02D10/32

Abstract: Methods and apparatuses are provided for avoiding cold translation lookaside buffer (TLB) misses in a computer system. A typical system is configured as a heterogeneous computing system having at least one central processing unit (CPU) and one or more graphic processing units (GPUs) that share a common memory address space. Each processing unit (CPU and GPU) has an independent TLB. When offloading a task from a particular CPU to a particular GPU, translation information is sent along with the task assignment. The translation information allows the GPU to load the address translation data into the TLB associated with the one or more GPUs prior to executing the task. Preloading the TLB of the GPUs reduces or avoids cold TLB misses that could otherwise occur without the benefits offered by the present disclosure.

Abstract translation: 提供了用于避免计算机系统中的冷翻译后备缓冲器（TLB）未命中的方法和装置。 典型的系统被配置为具有至少一个中央处理单元（CPU）和共享公共存储器地址空间的一个或多个图形处理单元（GPU）的异构计算系统。 每个处理单元（CPU和GPU）都有独立的TLB。 当将任务从特定CPU卸载到特定GPU时，将随任务分配一起发送翻译信息。 翻译信息允许GPU在执行任务之前将地址转换数据加载到与一个或多个GPU相关联的TLB中。 GPU的预加载减少或避免了在没有本公开提供的优点的情况下可能发生的冷TLB未命中。

公开(公告)号：WO2016033039A2

公开(公告)日：2016-03-03

申请号：PCT/US2015/046687

申请日：2015-08-25

Applicant: ADVANCED MICRO DEVICES, INC. ,  ATI TECHNOLOGIES ULC

Inventor： KEGEL, Andrew G. ,  ASARO, Anthony

IPC: G06F13/16 ,  G06F12/10

CPC classification number: G06F12/1081 ,  G06F12/02 ,  G06F12/1009 ,  G06F12/1027 ,  G06F13/28 ,  G06F2212/2532 ,  G06F2212/65 ,  G06F2212/68

Abstract: A device may receive a direct memory access request that identifies a virtual address. The device may determine whether the virtual address is within a particular range of virtual addresses. The device may selectively perform a first action or a second action based on determining whether the virtual address is within the particular range of virtual addresses. The first action may include causing a first address translation algorithm to be performed to translate the virtual address to a physical address associated with a memory device when the virtual address is not within the particular range of virtual addresses. The second action may include causing a second address translation algorithm to be performed to translate the virtual address to the physical address when the virtual address is within the particular range of virtual addresses. The second address translation algorithm may be different from the first address translation algorithm.

Abstract translation: 设备可以接收标识虚拟地址的直接存储器访问请求。 设备可以确定虚拟地址是否在虚拟地址的特定范围内。 设备可以基于确定虚拟地址是否在虚拟地址的特定范围内来选择性地执行第一动作或第二动作。 第一动作可以包括：当虚拟地址不在虚拟地址的特定范围内时，使第一地址转换算法执行以将虚拟地址转换为与存储器设备相关联的物理地址。 第二动作可以包括当虚拟地址在虚拟地址的特定范围内时使得执行第二地址转换算法以将虚拟地址转换为物理地址。 第二个地址转换算法可能与第一个地址转换算法不同。

公开(公告)号：WO2012009614A1

公开(公告)日：2012-01-19

申请号：PCT/US2011/044149

申请日：2011-07-15

Applicant: ADVANCED MICRO DEVICES, INC. ,  HUMMEL, Mark D. ,  KEGEL, Andrew G.

Inventor： HUMMEL, Mark D. ,  KEGEL, Andrew G.

IPC: G06F13/42 ,  G06F12/10

CPC classification number: G06F13/42 ,  G06F12/1081 ,  G06F2213/0026

Abstract: A page service request is received from a peripheral device requesting that a memory page be loaded into system memory. Page service request information corresponding to the received page service request is written as a queue entry into a queue structure in system memory. The processor is notified that the page request is present in the queue. The processor may be notified with an interrupt of a new queue entry. The processor processes the page service request and the peripheral device is notified of the completion of the processing of the request.

Abstract translation: 从外围设备接收到请求将存储器页面加载到系统存储器中的页面服务请求。 将与接收到的页面服务请求对应的页面服务请求信息作为队列条目写入系统存储器中的队列结构。 通知处理器页面请求存在于队列中。 处理器可能会被中断新的队列条目通知。 处理器处理页面服务请求，并且通知外围设备完成对请求的处理。

公开(公告)号：WO2017165520A1

公开(公告)日：2017-09-28

申请号：PCT/US2017/023592

申请日：2017-03-22

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： AWAD, Amro ,  BLAGODUROV, Sergey ,  BASU, Arkaprava ,  OSKIN, Mark H. ,  LOH, Gabriel H. ,  KEGEL, Andrew G. ,  CHRISTIE, David S. ,  MCGRATH, Kevin J.

IPC: G06F12/1027 ,  G06F12/0811

Abstract: The described embodiments include a computing device with two or more translation lookaside buffers (TLB). During operation, the computing device updates an entry in the TLB based on a virtual address to physical address translation and metadata from a page table entry that were acquired during a page table walk. The computing device then computes, based on a lease length expression, a lease length for the entry in the TLB. Next, the computing device sets, for the entry in the TLB, a lease value to the lease length, wherein the lease value represents a time until a lease for the entry in the TLB expires, wherein the entry in the TLB is invalid when the associated lease has expired. The computing device then uses the lease value to control operations that are allowed to be performed using information from the entry in the TLB.

Abstract translation: 所描述的实施例包括具有两个或更多个转换后备缓冲器（TLB）的计算设备。 在操作期间，计算设备基于虚拟地址到物理地址翻译来更新TLB中的条目，并且在页表行进期间获取来自页表条目的元数据。 计算设备然后基于租用长度表达式来计算TLB中的条目的租用长度。 接下来，对于TLB中的条目，计算设备将租赁值设置为租用长度，其中，租用值表示直到TLB中的条目的租约期满为止的时间，其中，当TLB中的条目 相关租约已过期。 计算设备然后使用该租赁值来控制允许使用来自TLB中的条目的信息来执行的操作。

公开(公告)号：WO2016040414A1

公开(公告)日：2016-03-17

申请号：PCT/US2015/049082

申请日：2015-09-09

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： KEGEL, Andrew G.

IPC: G06F13/14 ,  G06F9/455

CPC classification number: G06F13/102 ,  G06F9/4411 ,  G06F9/45558 ,  G06F2009/45579

Abstract: In a virtualized computer system without an IOMMU, all application IO requests must be processed by the guest operating system and by the hypervisor so that addresses are translated (twice) and validated (twice) properly. In a virtualized computer system with an IOMMU containing one "stage" of translation, the peripheral can safely be assigned directly to a guest OS because the IOMMU can be programmed to translate and check addresses issued by the device. As a result, route IO overhead due to hypervisor intervention can be eliminated. In one example, in a virtualized computer system with an IOMMU supporting two "stages" of translation, the peripheral can safely be assigned directly to an application within a guest OS. As a result, route IO overhead due to hypervisor and guest OS processing can be eliminated. This allows an application to achieve higher IO performance.

Abstract translation: 在没有IOMMU的虚拟化计算机系统中，所有应用程序IO请求必须由客户机操作系统和管理程序处理，以便地址被翻译（两次）并且被正确地验证（两次）。 在具有包含翻译“舞台”的IOMMU的虚拟化计算机系统中，可以将外围设备直接分配给客户操作系统，因为IOMMU可被编程为翻译和检查由设备发出的地址。 因此，可以消除由管理程序干预导致的路由IO开销。 在一个示例中，在具有支持翻译两个“阶段”的IOMMU的虚拟化计算机系统中，外围设备可以安全地直接分配给客户机OS内的应用。 因此，可以消除由管理程序和客户操作系统处理引起的路由IO开销。 这允许应用程序实现更高的IO性能。

公开(公告)号：WO2019099067A1

公开(公告)日：2019-05-23

申请号：PCT/US2018/042172

申请日：2018-07-13

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ROBERTS, David A. ,  KEGEL, Andrew G. ,  MEDNICK, Elliot H.

IPC: G06F15/78 ,  G06F9/48 ,  G06F9/50 ,  G06F17/50

Abstract: A macro scheduler includes a resource tracking module configured to update a database enumerating a plurality of macro components of a set of field programmable gate array (FPGA) devices, a communication interface configured to receive from a first client device a first design definition indicating one or more specified macro components for a design, resource allocation logic configured to allocate a first set of macro components for the design by allocating one of the plurality of macro components for each of the one or more specified macro components indicated in the first design definition, and configuration logic configured to implement the design in the set of FPGA devices by configuring the first set of allocated macro components according to the first design definition.

公开(公告)号：WO2017205204A1

公开(公告)日：2017-11-30

申请号：PCT/US2017/033514

申请日：2017-05-19

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： BLAGODUROV, Sergey ,  KEGEL, Andrew G.

IPC: G06F12/02

Abstract: The described embodiments include an input-output memory management unit (IOMMU) with two or more memory elements and a controller. The controller is configured to select, based on one or more factors, one or more selected memory elements from among the two or more memory elements for performing virtual address to physical address translations in the IOMMU. The controller then performs the virtual address to physical address translations using the one or more selected memory elements.

Abstract translation: 所描述的实施例包括具有两个或更多个存储器元件和控制器的输入输出存储器管理单元（IOMMU）。 控制器被配置为基于一个或多个因素来选择两个或更多个存储器元件中的一个或更多个选择的存储器元件，以用于在IOMMU中执行虚拟地址到物理地址转换。 控制器然后使用一个或多个选定的存储器元件来执行虚拟地址到物理地址转换。

公开(公告)号：WO2013003177A1

公开(公告)日：2013-01-03

申请号：PCT/US2012/043450

申请日：2012-06-21

Applicant: ADVANCED MICRO DEVICES, INC. ,  KEGEL, Andrew G. ,  GLASER, Stephen D.

Inventor： KEGEL, Andrew G. ,  GLASER, Stephen D.

IPC: G06F21/02

CPC classification number: G06F21/78

Abstract: A method includes updating contents of a value storage element indicating a number of occurrences of an event. The updating is based on contents of a match storage element storing event qualification information. The method includes providing the contents of the value storage element to a first software module executing on at least one processor. The providing is based on contents of a protect storage element indicating access information. In at least one embodiment, the method includes executing a first software module on the at least one processor in a first mode of operation. In at least one embodiment, the method includes executing a second software module on the at least one processor in a second mode of operation. In at least one embodiment, the second mode is more privileged than the first mode.

Abstract translation: 一种方法包括更新指示事件发生次数的值存储元件的内容。 该更新基于存储事件资格信息的匹配存储元件的内容。 该方法包括将值存储元件的内容提供给在至少一个处理器上执行的第一软件模块。 该提供基于指示访问信息的保护存储元件的内容。 在至少一个实施例中，该方法包括在第一操作模式下在所述至少一个处理器上执行第一软件模块。 在至少一个实施例中，该方法包括在第二操作模式下在所述至少一个处理器上执行第二软件模块。 在至少一个实施例中，第二模式比第一模式更具特权。