公开(公告)号：WO2017123284A1

公开(公告)日：2017-07-20

申请号：PCT/US2016/052769

申请日：2016-09-21

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： JAYASENA, Nuwan S. ,  ROBERTS, David A.

IPC: H01L23/00 ,  H01L25/065 ,  H01L23/12

CPC classification number: H01L23/49838 ,  H01L21/4853 ,  H01L23/145 ,  H01L23/147 ,  H01L23/15 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/50 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/81139 ,  H01L2224/8114 ,  H01L2225/06513 ,  H01L2225/06531 ,  H01L2225/06534 ,  H01L2225/06589 ,  H01L2225/06593 ,  H01L2924/1431 ,  H01L2924/1432 ,  H01L2924/1433 ,  H01L2924/1434 ,  H01L2924/1436 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/157 ,  H01L2924/15787 ,  H01L2924/1579 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/19105

Abstract: The described embodiments include an interposer with signal routes located therein. The interposer includes a set of sites arranged in a pattern, each site including a set of connection points. Each connection point in each site is coupled to a corresponding one of the signal routes. Integrated circuit chiplets may be mounted on the sites and signal connectors for mounted integrated circuit chiplets may coupled to some or all of the connection points for corresponding sites, thereby coupling the chiplets to corresponding signal routes. The chiplets may then send and receive signals via the connection points and signal routes. In some embodiments, the set of connection points in each of the sites is the same, i.e., has a same physical layout. In other embodiments, the set of connection points for each site is arranged in one of two or more physical layouts.

Abstract translation: 所描述的实施例包括具有位于其中的信号路由的中介层。 插入器包括按照图案排列的一组站点，每个站点包括一组连接点。 每个站点中的每个连接点都耦合到相应的一个信号路由。 集成电路小芯片可以安装在位置上，并且用于安装的集成电路小芯片的信号连接器可以耦合到对应位置的一些或全部连接点，从而将小芯片耦合到对应的信号路由。 小芯片然后可以经由连接点和信号路线发送和接收信号。 在一些实施例中，每个站点中的一组连接点是相同的，即具有相同的物理布局。 在其他实施例中，每个站点的连接点集合被布置在两个或更多个物理布局中的一个中。

公开(公告)号：WO2017184497A1

公开(公告)日：2017-10-26

申请号：PCT/US2017/027901

申请日：2017-04-17

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ROBERTS, David A. ,  IGNATOWSKI, Michael

IPC: G06F13/16 ,  G06F12/02

Abstract: Described are a method and processing apparatus to tag and track objects related to memory allocation calls. An application or software adds a tag to a memory allocation call to enable object level tracking. An entry is made into an object tracking table, which stores the tag and a variety of statistics related to the object and associated memory devices. The object statistics may be queried by the application to tune power/performance characteristics either by the application making runtime placement decisions, or by off-line code tuning based on a previous run. The application may add a tag to a memory allocation call to specify the type of memory characteristics requested based on the object statistics.

Abstract translation: 描述了一种标记和跟踪与内存分配调用相关的对象的方法和处理装置。 应用程序或软件将标记添加到内存分配调用中以启用对象级别跟踪。 将一个条目写入对象跟踪表中，该表格存储标签以及与对象和相关存储器设备有关的各种统计信息。 应用程序可以通过应用程序查询对象统计信息来调整功耗/性能特征，或者通过应用程序进行运行时放置决策，或者通过基于前一次运行的离线代码调整。 应用程序可以为内存分配调用添加一个标记，以根据对象统计信息指定请求的内存特征类型。

公开(公告)号：WO2019027554A1

公开(公告)日：2019-02-07

申请号：PCT/US2018/035377

申请日：2018-05-31

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： KEGEL, Andrew G. ,  ROBERTS, David A.

IPC: G06F9/50

Abstract: Systems, apparatuses, and methods for sharing an field programmable gate array compute engine are disclosed. A system includes one or more processors and one or more FPGAs. The system receives a request, generated by a first user process, to allocate a portion of processing resources on a first FPGA. The system maps the portion of processing resources of the first FPGA into an address space of the first user process. The system prevents other user processes from accessing the portion of processing resources of the first FPGA. Later, the system detects a release of the portion of the processing resources on the first FPGA by the first user process. Then, the system receives a second request to allocate the first FPGA from a second user process. In response to the second request, the system maps the first FPGA into an address space of the second user process.

公开(公告)号：WO2016209406A1

公开(公告)日：2016-12-29

申请号：PCT/US2016/032504

申请日：2016-05-13

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ROBERTS, David A.

IPC: G06F15/78

CPC classification number: H03K19/17728 ,  G06F15/7892 ,  H03K19/0008 ,  H03K19/1776 ,  H03K19/17776

Abstract: A programmable device comprises one or more programming regions, each comprising a plurality of configurable logic blocks, where each of the plurality of configurable logic blocks is selectively connectable to any other configurable logic block via a programmable interconnect fabric. The programmable device further comprises configuration logic configured to, in response to an instruction in an instruction stream, reconfigure hardware in one or more of the configurable logic blocks in a programming region independently from any of the other programming regions.

Abstract translation: 可编程设备包括一个或多个编程区域，每个编程区域包括多个可配置逻辑块，其中多个可配置逻辑块中的每一个可经由可编程互连结构选择性地连接到任何其它可配置逻辑块。 可编程设备还包括配置逻辑，配置为响应于指令流中的指令，在编程区域中的一个或多个可配置逻辑块中独立于任何其他编程区域重新配置硬件。

公开(公告)号：WO2019099067A1

公开(公告)日：2019-05-23

申请号：PCT/US2018/042172

申请日：2018-07-13

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ROBERTS, David A. ,  KEGEL, Andrew G. ,  MEDNICK, Elliot H.

IPC: G06F15/78 ,  G06F9/48 ,  G06F9/50 ,  G06F17/50

Abstract: A macro scheduler includes a resource tracking module configured to update a database enumerating a plurality of macro components of a set of field programmable gate array (FPGA) devices, a communication interface configured to receive from a first client device a first design definition indicating one or more specified macro components for a design, resource allocation logic configured to allocate a first set of macro components for the design by allocating one of the plurality of macro components for each of the one or more specified macro components indicated in the first design definition, and configuration logic configured to implement the design in the set of FPGA devices by configuring the first set of allocated macro components according to the first design definition.

公开(公告)号：WO2019094105A1

公开(公告)日：2019-05-16

申请号：PCT/US2018/051373

申请日：2018-09-17

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： CHENG, Kevin Y. ,  ROBERTS, David A. ,  BRANTLEY, William C.

IPC: G06F15/78

CPC classification number: G06F9/461 ,  G06F9/5016 ,  G06F13/4022 ,  G06F13/4282 ,  G06F15/7871 ,  G06F2213/0026

Abstract: A hardware context manager in a field-programmable gate array (FPGA) device includes configuration logic configured to program one or more programming regions in the FPGA device based on configuration data for implementing a target configuration of the one or more programming regions. Context management logic in the hardware context manager is coupled with the configuration logic and saves a first context corresponding to the target configuration by retrieving first state information from the set of one or more programming regions, where the first state information is generated based on the target configuration, and storing the retrieved first state information in a context memory. The context management logic restores the first context by transferring the first state information from the context memory to the one or more programming regions, and causing the configuration logic to program the one or more programming regions based on the configuration data.