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    DUPLICATED REGISTERS IN CHIPLET PROCESSING UNITS
    1.
    发明申请
    DUPLICATED REGISTERS IN CHIPLET PROCESSING UNITS 审中-公开

    公开(公告)号：WO2023064728A1

    公开(公告)日：2023-04-20

    申请号：PCT/US2022/077848

    申请日：2022-10-10

    Applicant: ADVANCED MICRO DEVICES, INC. ,  ATI TECHNOLOGIES ULC

    Inventor： DONG, HaiKun ,  CHRISTIDIS, Kostantinos Danny ,  WANG, Ling-Ling ,  WU, MinHua ,  CONG, Gaojian ,  WANG, Rui

    IPC: G06F11/00

    Abstract: Systems, apparatuses, and methods for implementing duplicated registers for access by initiators across multiple semiconductor dies are disclosed. A system includes multiple initiators on multiple semiconductor dies of a chiplet processor. One of the semiconductor dies is the master die, and this master die has copies of registers which can be accessed by the multiple initiators on the multiple semiconductor dies. When a given initiator on a given secondary die generates a register access, the register access is routed to the master die and a particular duplicate copy of the register maintained for the given secondary die. From the point of view of software, the multiple semiconductor dies appear as a single die, and the multiple initiators appear as a single initiator. Multiple types of registers can be maintained by the master die, with a flush register being one of the register types.

    PERFORMING ASYNCHRONOUS MEMORY CLOCK CHANGES ON MULTI-DISPLAY SYSTEMS
    4.
    发明申请
    PERFORMING ASYNCHRONOUS MEMORY CLOCK CHANGES ON MULTI-DISPLAY SYSTEMS 审中-公开

    公开(公告)号：WO2022137046A1

    公开(公告)日：2022-06-30

    申请号：PCT/IB2021/061867

    申请日：2021-12-16

    Applicant: ATI TECHNOLOGIES ULC

    Inventor： RAHMAN, Arshad ,  PANCHACHARAMOORTHY, Rajeevan ,  IVANOVIC, Boris

    IPC: G09G5/12

    Abstract: Systems, apparatuses, and methods for performing asynchronous memory clock changes on multiple displays are disclosed. From time to time, a memory clock frequency change is desired for a memory subsystem storing frame buffer(s) used to drive pixels to multiple displays. For example, when the real-time memory bandwidth demand differs from the memory bandwidth available with the existing memory clock frequency, a control unit tracks the vertical blanking interval (VBI) timing of a first display. Also, the control unit causes a second display to enter into panel self-refresh (PSR) mode. Once the PSR mode of the second display overlaps with a VBI of the first display, a memory clock frequency change, including memory training, is initiated. After the memory clock frequency change, the displays are driven by the frame buffer(s) in the memory subsystem at an updated frequency.

    HARDWARE-BASED PROTECTION OF VIRTUAL FUNCTION RESOURCES
    5.
    发明申请
    HARDWARE-BASED PROTECTION OF VIRTUAL FUNCTION RESOURCES 审中-公开

    公开(公告)号：WO2022123450A1

    公开(公告)日：2022-06-16

    申请号：PCT/IB2021/061430

    申请日：2021-12-07

    Applicant: ATI TECHNOLOGIES ULC [CA]/[CA]

    Inventor： JIANG, Yinan ,  ZHANG, Min

    IPC: G06F9/44 ,  G06F9/455

    Abstract: Virtual functions are implemented using a plurality of resources [220] and physical function circuitry [210] that executes a virtual function [215] using information stored in the plurality of resources. A processing unit [105] executes a host driver [205] that selectively enables access to the plurality of resources by the virtual function based on an operational state of the processing unit. In some cases, a state machine [300] that determines a state of the virtual function and the host driver that enables access to the plurality of resources by the virtual function based on the state of the virtual function executing on the processing unit. The subsets of the plurality of resources are used to implement a frame buffer [222], one or more context registers [225, 226], a doorbell [231], and one or more mailbox registers [235, 236].

    APPLICATION OVERRIDE OF POWER ESTIMATION MECHANISM
    6.
    发明申请
    APPLICATION OVERRIDE OF POWER ESTIMATION MECHANISM 审中-公开

    公开(公告)号：WO2022103879A1

    公开(公告)日：2022-05-19

    申请号：PCT/US2021/058840

    申请日：2021-11-10

    Applicant: ADVANCED MICRO DEVICES, INC. ,  ATI TECHNOLOGIES ULC

    Inventor： HAUKE, Jonathan David ,  CLARK, Adam

    IPC: G06F1/3206 ,  G06F1/324 ,  G06F1/3296

    Abstract: Systems, apparatuses, and methods for performing a software override of a power estimation mechanism are disclosed. A computing system includes a plurality of tuned parameters for generating an estimate of power consumption. The tuned parameters are generated based on post-silicon characterization of the system. After deployment, the system executes a plurality of different applications. When launching a particular application, the system loads a corresponding set of override parameters which are used to replace the plurality of tuned parameters. The system generates an estimate of power consumption using the set of override parameters rather than the previously determined tuned parameters. Then while executing the particular application, the system makes adjustments to power and frequency values for the various system components based on the estimate of power consumption.

    SECURE BUFFER FOR BOOTLOADER
    9.
    发明申请
    SECURE BUFFER FOR BOOTLOADER 审中-公开

    公开(公告)号：WO2021061967A1

    公开(公告)日：2021-04-01

    申请号：PCT/US2020/052471

    申请日：2020-09-24

    Applicant: ADVANCED MICRO DEVICES, INC. ,  ATI TECHNOLOGIES ULC

    Inventor： RAO, Murali ,  IP, Clarence ,  SCANLON, Joseph ,  DOCTOR, Mihir S. ,  STEWART, Norman ,  KRISHNAN, Guhan

    IPC: G06F21/57 ,  G06F21/53 ,  G06F21/64

    Abstract: A processing system isolates at a physically or logically separate memory region of a processing unit boot code that is received from an external boot source for programming a boot memory of the processing unit until after the boot code is validated to protect against buffer overruns that could compromise the processing system. The processing unit includes a secure buffer region of memory that is physically or logically isolated from the remainder of the processing unit for receiving boot code from an external boot source such as a personal computer (PC) such that any buffer overruns at the secure buffer simply overwrite data stored at the secure buffer, and do not affect data or instructions that are executing at the processing unit.

    SAFETY MONITOR FOR IMAGE MISCLASSIFICATION
    10.
    发明申请
    SAFETY MONITOR FOR IMAGE MISCLASSIFICATION 审中-公开

    公开(公告)号：WO2020240315A1

    公开(公告)日：2020-12-03

    申请号：PCT/IB2020/054448

    申请日：2020-05-11

    Applicant: ATI TECHNOLOGIES ULC

    Inventor： KWONG, Tung Chuen ,  CHAN, Benjamin Koon Pan ,  PORPINO SOBREIRA MARQUES, David ,  IP, Clarence ,  YU, Hung Wilson

    IPC: G06K9/62 ,  G06F11/30 ,  G06N3/02 ,  G06T7/00

    Abstract: Systems, apparatuses, and methods for implementing a safety monitor framework for a safety-critical inference application are disclosed. A system includes a safety-critical inference application, a safety monitor, and an inference accelerator engine. The safety monitor receives an input image, test data, and a neural network specification from the safety-critical inference application. The safety monitor generates a modified image by adding additional objects outside of the input image. The safety monitor provides the modified image and neural network specification to the inference accelerator engine which processes the modified image and provides outputs to the safety monitor. The safety monitor determines the likelihood of erroneous processing of the original input image by comparing the outputs for the additional objects with a known good result. The safety monitor complements the overall fault coverage of the inference accelerator engine and covers faults only observable at the network level.

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