公开(公告)号：WO2003021614A1

公开(公告)日：2003-03-13

申请号：PCT/US2002/028100

申请日：2002-09-05

Applicant: AVX CORPORATION

Inventor： GALVAGNI, John, L. ,  HEISTAND, Robert, II ,  KORONY, Gheorghe

IPC: H01G4/00

CPC classification number: H01G4/228 ,  H01G2/00 ,  H01G4/30 ,  H01G4/385 ,  H01L23/642 ,  H01L2924/0002 ,  H01L2924/09701 ,  H01L2924/3011 ,  Y10T29/43 ,  Y10T29/435 ,  Y10T29/49082 ,  Y10T29/49124 ,  Y10T29/49128 ,  Y10T29/4913 ,  H01L2924/00

Abstract: Multi-layer and cascade capacitors for use in high frequency applications and other environments are disclosed. The subject capacitor may comprise multiple capacitor components (10) or aspects thereof in an integrated package. Such components may include, for example thin film BGA components, interdigitated capacitor (IDC) configurations, double-layer electrochemical capacitors, single layer capacitors and others. Exemplary embodiments of the present subject matter preferably encompass at least certain aspects of thin film BGA techniques and/or IDC-style configurations. Features for attachment and interconnection are provided that facilitate low ESL while maintaining a given capacitance value. Additional advantages include low ESL and decoupling performance over a broad band of operational frequencies. More particularly, the presently disclosed technology provides for exemplary capacitors that may function over a frequency range from kilohertz up to several gigahertz, and that may also be characterized by a wide range of capacitance values. An additionally disclosed feature of the present subject matter is to incorporate dielectric layers (22) of varied thicknesses to broaden the resonancy curve associated with a particular configuration.

Abstract translation: 公开了用于高频应用和其他环境的多层和级联电容器。 本发明电容器可以包括多个电容器组件（10）或其集成封装的方面。 这样的组件可以包括例如薄膜BGA组件，交叉电容器（IDC）配置，双层电化学电容器，单层电容器等。 本主题的示例性实施例优选地包括薄膜BGA技术和/或IDC式配置的至少某些方面。 提供用于附接和互连的特征，其在保持给定的电容值的同时促进低ESL。 另外的优点包括在宽频带工作频率下的低ESL和去耦性能。 更具体地，本公开的技术提供了可以在从千赫兹到几千兆赫兹的频率范围内起作用的示例性电容器，并且还可以通过宽范围的电容值来表征。 本主题的另外公开的特征是结合不同厚度的电介质层（22）以扩大与特定配置相关联的共振曲线。

公开(公告)号：WO2021231132A1

公开(公告)日：2021-11-18

申请号：PCT/US2021/030620

申请日：2021-05-04

Applicant: AVX CORPORATION

Inventor： NELSON, Cory ,  KORONY, Gheorghe

IPC: H03H9/02 ,  H03H9/72

Abstract: A filter can include a monolithic substrate and at least one conductive layer formed over a top surface of the monolithic substrate and along at least a portion of one or more of a first top edge of the monolithic substrate or a second top edge of the monolithic substrate. A cover layer can be arranged over the top surface of the monolithic substrate. A shield layer can connect with one or more of the conductive layer(s) at the first top edge or the second top edge of the monolithic substrate. The shield layer can include a first portion formed over the first side surface of the cover layer, a second portion formed over the top surface of the cover layer, and a third portion formed over the second side surface of the cover layer.

公开(公告)号：WO2019236683A1

公开(公告)日：2019-12-12

申请号：PCT/US2019/035549

申请日：2019-06-05

Applicant: AVX CORPORATION

Inventor： NELSON, Cory ,  KORONY, Gheorghe

IPC: H01C1/084 ,  H01C1/014 ,  H01C7/00 ,  H01C17/28

Abstract: A surface mount component is disclosed including an electrically insulating beam that is thermally conductive. The electrically insulating beam has a first end and a second end that is opposite the first end. The surface mount component includes a thin-film component formed on the electrically insulating beam adjacent the first end of the electrically insulating beam. A heat sink terminal is formed on the electrically insulating beam adjacent a second end of the electrically insulating beam. In some embodiments, the thin-film component has an area power capacity of greater than about 0.17 W/mm 2 at about 28 GHz.

公开(公告)号：WO2002101772A1

公开(公告)日：2002-12-19

申请号：PCT/US2002/017221

申请日：2002-06-03

Applicant: AVX CORPORATION

Inventor： GALVAGNI, John, L. ,  RITTER, Andrew ,  KORONY, Gheorghe ,  BROWN, Sonja

IPC: H01G4/30

CPC classification number: H01G2/065 ,  H01G4/232 ,  H01L23/642 ,  H01L2924/0002 ,  H05K1/0231 ,  H01L2924/00

Abstract: An improved low inductance termination scheme is disclosed for grid array capacitors. The enhanced termination scheme provides for shorter termination length and leaves the sides of a capacitive element free from any structure. The area typically taken up by solder lans is reduced, facilitating much closer chip spacing on a circuit board. The arrangement generally includes interleaved dielectric and electrode layers (10) in an interdigitated configuration. Vias are drilled through tabs (14) extending from selected or the electrode layers (10), and then filled with suitable conductive material. Solder balls (24) may be applied directly to this conductive material, providing a ball grid array (BGA) packaged chip ready to mount on an IC and reflow. Composition of such solder balls (24) is easily varied to comply with specific firing conditions. Such capacitor chips are also compatible with land grid array (LGA) packaging techniques. The subject interdigitated electrode design may be utilized to form a single multilayer capacitor or multiple discrete capacitors (30). Such a capacitor array may be formed by retaining the external configuration and internally subdividing the electrodes (10). The resulting low cost, low inductance capacitor is ideal for many high frequency applications requiring decoupling capacitors.

Abstract translation: 公开了一种用于栅格阵列电容器的改进的低电感端接方案。 增强的端接方案提供较短的端接长度并使得电容元件的侧面没有任何结构。 通常由焊锡焊盘占据的面积减小，有助于电路板上的芯片间距更小。 该装置通常包括交叉配置的交错电介质层和电极层（10）。 通过从选定的或电极层（10）延伸的突片（14）钻出通孔，然后用合适的导电材料填充。 可以将焊球（24）直接施加到该导电材料上，提供准备安装在IC上并回流的球栅阵列（BGA）封装芯片。 这种焊球（24）的组成容易变化以符合特定的烧制条件。 这种电容器芯片也与陆地网格阵列（LGA）封装技术兼容。 主题交叉电极设计可用于形成单个层叠电容器或多个分立电容器（30）。 这样的电容器阵列可以通过保持外部配置并且在内部细分电极（10）来形成。 所产生的低成本低电感电容对于需要去耦电容器的许多高频应用是理想的。