公开(公告)号：WO1993008525A2

公开(公告)日：1993-04-29

申请号：PCT/US1992009065

申请日：1992-10-22

Applicant: INTEL CORPORATION

Inventor： INTEL CORPORATION ,  SPRAGUE, David, Leroy ,  HARNEY, Kevin ,  KOWASHI, Eiichi ,  KEITH, Michael ,  SIMON, Allen, Henry ,  PAPADOPOULOS, Gregory, Michael ,  HAYS, Walter, Patrick ,  SALEM, George, Francis ,  SHIUE, Shih-Wei ,  BERTAPELLI, Anthony, Paul ,  SHILMAN, Vitaly, Haskel

IPC: G06F09/30

CPC classification number: G06F9/3885 ,  G06F9/30072 ,  G06F9/30149 ,  G06F9/3802 ,  G06F9/3863

Abstract: Single-instruction multiple-data is a new class of integrated video signal processors especially suited for real-time processing of two-dimensional images. The single-instruction, multiple-data architecture is adopted to exploit the high degree of parallelism inherent in many video signal processing algorithms. Features have been added to the architecture which support conditional execution and sequencing - an inherent limitation of traditional single-instruction multiple-data machines. A separate transfer engine offloads transaction processing from the execution core, allowing balancing of input/output and compute resources - a critical factor in optimizing performance for video processing. These features, coupled with a scalable architecture allow a united programming model and application driven performance.

Abstract translation: 单指令多数据是一类新的集成视频信号处理器，特别适用于二维图像的实时处理。 采用单指令多数据架构来开发许多视频信号处理算法中固有的高度并行度。 特性已被添加到支持条件执行和排序的架构中，这是传统单指令多数据计算机的固有局限性。 单独的传输引擎从执行核心中卸载事务处理，允许平衡输入/输出和计算资源 - 这是影响视频处理性能的关键因素。 这些功能与可扩展架构相结合，可以实现统一的编程模型和应用驱动的性能。

公开(公告)号：WO1992015065A1

公开(公告)日：1992-09-03

申请号：PCT/US1992000902

申请日：1992-02-05

Applicant: INTEL CORPORATION

Inventor： INTEL CORPORATION ,  SPRAGUE, David, Leroy

IPC: G06F15/353

CPC classification number: G06F17/17 ,  G06F7/5272 ,  G06F7/544

Abstract: An interpolator array having a plurality of interpolator array cells is provided for receiving first and second input values to be interpolated and an interpolator weight term, to provide an interpolated output. A bit of each of the two input values to be interpolated is received by an interpolator array cell and applied to a selecting circuit within a cell of the interpolator array. Additionally, an interpolation weight bit of the interpolation weight term is applied to the selection circuit. The selecting circuit applies either the input bit of the first input value or the input bit of the second input value to an adder within the interpolator cell in accordance with the value of the interpolation weight bit. An interpolator array cell also receives a partial product input and a carry-in input and applies these additional inputs to the adder. The adder provides a partial product output and a carry-out in accordance with the applied inputs.

公开(公告)号：WO1989009516A1

公开(公告)日：1989-10-05

申请号：PCT/US1989001302

申请日：1989-03-29

Applicant: INTEL CORPORATION

Inventor： INTEL CORPORATION ,  SPRAGUE, David, Leroy ,  SIMON, Allen, Henry

IPC: H03M07/42

CPC classification number: H03M7/425

Abstract: Digital image data is encoded using a variable-length code which is described by a group of parameter values. Each parameter value describes a set of code values; each code value corresponds to a possible value of the data which is to be encoded. When the data is encoded, the parameter values are appended to the encoded data. A decoder stores the parameter values into a memory and then combines data values derived from the encoded data with parameter values from the memory to generate decoded data values. Each code word includes a prefix which indicates a number of successive parameter values which are to be summed, and a population index which is to be added to the summed parameter values to produce a decoded data value.