公开(公告)号：WO1998022872A1

公开(公告)日：1998-05-28

申请号：PCT/IB1997001340

申请日：1997-10-27

Applicant: PHILIPS ELECTRONICS N.V. ,  PHILIPS NORDEN AB

Inventor： PHILIPS ELECTRONICS N.V. ,  PHILIPS NORDEN AB ,  GLOOR, Daniel ,  GRADENWITZ, Paul, Georg, Mechion ,  STEGMANN, Gerhard ,  BAUMANN, Daniel

IPC: G06F09/30

CPC classification number: G06F9/3871 ,  G06F1/3203

Abstract: The data processing circuit has a self-timed instruction execution unit, which operates asynchronously, signalling the completion of processes and starting subsequent processes in response to such signalling. In order to satisfy real time constraints upon program execution ready signals generated after completion of selected instructions are gated with a timer signal before they are used to start a next instruction. In an embodiment, the amount of time left between the ready signal is used to start a next instruction is measured and used to regulate a power supply voltage of the instruction execution unit so that it is just high enough to make the instruction execution unit sufficiently fast to meet the real time constraints.

Abstract translation: 数据处理电路具有自动运行的指令执行单元，其异步操作，响应于这种信令而发信号通知过程的完成和开始后续处理。 为了满足程序执行时的实时约束，在选择的指令完成之后产生的就绪信号在用于开始下一条指令之前被定时器信号选通。 在一个实施例中，测量准备信号之间留下的时间量用于开始下一条指令，并用于调节指令执行单元的电源电压，使得它足够高以使指令执行单元足够快 满足实时限制。

公开(公告)号：WO1997042565A1

公开(公告)日：1997-11-13

申请号：PCT/US1997002330

申请日：1997-02-18

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ADVANCED MICRO DEVICES, INC. ,  BARTKOWIAK, John, G.

IPC: G06F09/30

CPC classification number: G06F9/30141 ,  G06F9/3885

Abstract: A DSP including a register file connected to data memories and functional units is provided. Functional units read operands from the register file and store results into the register file. Various register storage locations from communicative links between the functional units and the memories, in accordance with a particular code sequence being executed by the DSP. Because each functional unit has an independent path to the register file, each functional unit may provide results to the register file concurrently. Additionally, having multiple register storage locations which are accessible to any functional unit permits flexibility in the operation of the DSP. Multiple register storage locations may be used by the same functional unit, allowing program code to be more optimized by storing values for later use in one of the register storage locations, as opposed to storing values in the data memories. The register file essentially provides a buffer between the functional units, and between the functional units and memory.

Abstract translation: 提供了包括连接到数据存储器和功能单元的寄存器文件的DSP。 功能单元从寄存器文件中读取操作数，并将结果存储到寄存器文件中。 根据由DSP执行的特定代码序列，功能单元和存储器之间的通信链路的各种寄存器存储位置。 因为每个功能单元具有到寄存器文件的独立路径，所以每个功能单元可以同时向寄存器文件提供结果。 此外，具有可由任何功能单元访问的多个寄存器存储单元允许DSP的操作的灵活性。 多个寄存器存储位置可以由相同的功能单元使用，通过将值存储在一个寄存器存储位置中，以便将数据存储在数据存储器中，从而允许程序代码被更优化以供稍后使用。 寄存器文件本质上在功能单元之间以及功能单元和存储器之间提供缓冲器。

公开(公告)号：WO1997014093A1

公开(公告)日：1997-04-17

申请号：PCT/JP1996002910

申请日：1996-10-07

Applicant: HITACHI, LTD. ,  NAKAGAWA, Tetsuya ,  HATANO, Yuji ,  SAGESAKA, Yasuhiro ,  BAJI, Toru ,  NOGUCHI, Koki

Inventor： HITACHI, LTD.

IPC: G06F09/30

CPC classification number: G06F9/3885 ,  G06F1/3203 ,  G06F15/7807

Abstract: For manufacturing a mobile communication terminal, reduction of the cost, power consumption, and size is a very important factor, and it is a major problem for the conventional technique in which two independent sets of DSPs and CPUs are used, because two systems of external memories are required. Further, since two systems of peripheral devices for data input/output are necessary for the DSPs and CPUs, there exists useless overhead between the DSPs and CPUs. A mobile communication terminal system is realized by using an integrated DSP/CPU chip having a DSP/CPU core (500) integrated as a single bus master, an integrated external bus interface (606) and an integrated peripheral circuit interface. Therefore, an inexpensive, low-power consumption, small-sized mobile communication terminal system is provided because the memory systems and peripheral circuits of the DSPs and CPUs are integrated.

Abstract translation: 对于制造移动通信终端，成本，功耗和尺寸的降低是非常重要的因素，对于使用两个独立的DSP和CPU组的传统技术来说，这是一个主要问题，因为两个外部系统 需要回忆 此外，由于用于数据输入/输出的外围设备的两个系统对于DSP和CPU是必要的，所以在DSP和CPU之间存在无用的开销。 通过使用具有集成为单总线主机的DSP / CPU核心（500），集成外部总线接口（606）和集成外围电路接口的集成DSP / CPU芯片来实现移动通信终端系统。 因此，由于DSP和CPU的存储器系统和外围电路被集成，所以提供了廉价的低功耗小型移动通信终端系统。

公开(公告)号：WO1997013193A1

公开(公告)日：1997-04-10

申请号：PCT/US1996015417

申请日：1996-10-03

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ADVANCED MICRO DEVICES, INC. ,  FAVOR, John, G.

IPC: G06F09/30

CPC classification number: G06F9/382 ,  G06F9/30152 ,  G06F9/30174 ,  G06F9/3806 ,  G06F9/3812 ,  G06F9/3816 ,  G06F9/3822 ,  G06F9/3853

Abstract: Variable-length instructions are prepared for simultaneous decoding and execution of a plurality of instructions in parallel by reading multiple variable-length instructions from an instruction source and determining the starting point of each instruction so that multiple instructions are presented to a decoder simultaneously for decoding in parallel. Immediately upon accessing the multiple variable-length instructions from an instruction memory, a predecoder derives predecode information for each byte of the variable-length instructions by determining an instruction length indication for that byte, assuming each byte to be an opcode byte since the actual opcode byte is not identified. The predecoder associates an instruction length to each instruction byte. The instructions and predecode information are applied to an instruction buffer circuit in a memory-aligned format. The instruction buffer circuit prepares the variable-length instructions for decoding by converting the instruction alignment from a memory alignment to an instruction alignment on the basis of the instruction length indication. The instruction buffer circuit also assists the preparation of variable-length instructions for decoding of multiple instructions in parallel by facilitating a conversion of the instruction length indication to an instruction pointer.

Abstract translation: 准备可变长度指令，以通过从指令源读取多个可变长度指令并且确定每个指令的起始点来并行地同时解码和执行多个指令，以便同时向解码器呈现多个指令以进行解码 平行。 在从指令存储器访问多个可变长度指令时，预解码器立即通过确定该字节的指令长度指示来导出可变长度指令的每个字节的预解码信息，假设每个字节作为操作码字节，因为实际操作码 字节未被识别。 预解码器将指令长度与每个指令字节相关联。 指令和预解码信息以存储器对准的格式应用于指令缓冲器电路。 指令缓冲器电路根据指令长度指示，通过将指令对准从存储器对准转换为指令对准来准备用于解码的可变长度指令。 指令缓冲器电路还通过促进将指令长度指示转换为指令指针来协助准备用于并行解码多个指令的可变长度指令。

公开(公告)号：WO1996008762A2

公开(公告)日：1996-03-21

申请号：PCT/IB1995000667

申请日：1995-08-21

Applicant: PHILIPS ELECTRONICS N.V. ,  PHILIPS NORDEN AB

Inventor： PHILIPS ELECTRONICS N.V. ,  PHILIPS NORDEN AB ,  MIZRAHI-SHALOM, Ori ,  KO, Kung-Ling

IPC: G06F09/30

CPC classification number: G06F9/324 ,  G06F9/30149 ,  G06F9/321 ,  G06F9/322 ,  G06F9/3804 ,  G06F9/3806 ,  G06F9/3816

Abstract: A microcontroller or processor architecture that performs word aligned multibyte fetches but allows byte aligned instructions. Jump target addresses are word aligned, resulting in a word aligned fetch of the jump-to instruction. An assembler or compiler loads code into an instruction memory with branch instruction target addresses aligned on word boundaries. Returns from interrupts load the program counter with the complete return address which is byte aligned.

Abstract translation: 执行字对齐多字节读取但允许字节对齐指令的微控制器或处理器架构。 跳转目标地址是字对齐的，导致跳转到指令的字对齐获取。 汇编器或编译器将代码加载到指令存储器中，其中分支指令目标地址在字边界上对齐。 从中断返回使用字节对齐的完整返回地址加载程序计数器。

公开(公告)号：WO1993020504A1

公开(公告)日：1993-10-14

申请号：PCT/US1993002902

申请日：1993-03-26

Applicant: CENTRAL POINT SOFTWARE, INC.

Inventor： CENTRAL POINT SOFTWARE, INC. ,  BLOMFIELD-BROWN, Christopher

IPC: G06F09/30

CPC classification number: G06F9/445 ,  G06F9/451

Abstract: A management system for memory resident computer programs is disclosed which serves to provide compatibility between memory resident programs, TSR's, written for the DOS operating system and the Windows graphical user interface whereby graphical images are generated and displayed to the user running the Windows graphical user interface under the command of a DOS TSR and the user's input data may be communicated back to the DOS TSR in response to the image displayed. The present invention is comprised of a DOS TSR and a Windows TSR Manager which allocates memory addressable by both the DOS TSR and the Windows TSR Manager such that a communication channel independent of the DOS and Windows user interfaces is established and where the Windows TSR Manager further includes a Windows TSR Library Handler and one or more Windows TSR Libraries one for each DOS TSR supported by the present management system which serves to generate graphical images compatible with the Windows graphical user interface.

公开(公告)号：WO1993008525A2

公开(公告)日：1993-04-29

申请号：PCT/US1992009065

申请日：1992-10-22

Applicant: INTEL CORPORATION

Inventor： INTEL CORPORATION ,  SPRAGUE, David, Leroy ,  HARNEY, Kevin ,  KOWASHI, Eiichi ,  KEITH, Michael ,  SIMON, Allen, Henry ,  PAPADOPOULOS, Gregory, Michael ,  HAYS, Walter, Patrick ,  SALEM, George, Francis ,  SHIUE, Shih-Wei ,  BERTAPELLI, Anthony, Paul ,  SHILMAN, Vitaly, Haskel

IPC: G06F09/30

CPC classification number: G06F9/3885 ,  G06F9/30072 ,  G06F9/30149 ,  G06F9/3802 ,  G06F9/3863

Abstract: Single-instruction multiple-data is a new class of integrated video signal processors especially suited for real-time processing of two-dimensional images. The single-instruction, multiple-data architecture is adopted to exploit the high degree of parallelism inherent in many video signal processing algorithms. Features have been added to the architecture which support conditional execution and sequencing - an inherent limitation of traditional single-instruction multiple-data machines. A separate transfer engine offloads transaction processing from the execution core, allowing balancing of input/output and compute resources - a critical factor in optimizing performance for video processing. These features, coupled with a scalable architecture allow a united programming model and application driven performance.

Abstract translation: 单指令多数据是一类新的集成视频信号处理器，特别适用于二维图像的实时处理。 采用单指令多数据架构来开发许多视频信号处理算法中固有的高度并行度。 特性已被添加到支持条件执行和排序的架构中，这是传统单指令多数据计算机的固有局限性。 单独的传输引擎从执行核心中卸载事务处理，允许平衡输入/输出和计算资源 - 这是影响视频处理性能的关键因素。 这些功能与可扩展架构相结合，可以实现统一的编程模型和应用驱动的性能。

公开(公告)号：WO1990001192A1

公开(公告)日：1990-02-08

申请号：PCT/US1989003044

申请日：1989-07-18

Applicant: UNITED STATES DEPARTMENT OF ENERGY

Inventor： UNITED STATES DEPARTMENT OF ENERGY ,  DAVIDSON, George, Sidney ,  GRAFE, Victor, Gerald

IPC: G06F09/30

CPC classification number: G06F9/4494

Abstract: A data flow computer and method of computing is disclosed which utilizes a data driven processor node architecture. The apparatus in a preferred embodiment includes a plurality of First-In-First-Out (FIFO) registers, a plurality of related data flow memories, and a processor. The processor makes the necessary calculations and includes a control unit to generate signals to enable the appropriate FIFO register receiving the result. In a particular embodiment, there are three FIFO registers per node: an input FIFO register to receive input information form an outside source and provide it to the data flow memories; an output FIFO register to provide output information from the processor to an outside recipient; and an internal FIFO register to provide information from the processor back to the data flow memories. The data flow memories are comprised of four commonly addressed memories. A parameter memory holds the A and B parameters used in the calculations; an opcode memory holds the instruction; a target memory holds the output adress; and a tag memory contains status bits for each parameter. One status bit indicates whether the corresponding parameter is in the parameter memory and one status but to indicate whether the stored information in the corresponding data parameter is to be reused. The tag memory outputs a ''fire'' signal (signal R VALID) when all of the necessary information has been stored in the data flow memories, and thus when the instruction is ready to be fired to the processor.

Abstract translation: 公开了一种利用数据驱动的处理器节点架构的数据流计算机和计算方法。 优选实施例中的装置包括多个先进先出（FIFO）寄存器，多个相关数据流存储器和处理器。 处理器进行必要的计算，并包括一个控制单元来产生信号，使相应的FIFO寄存器能够接收结果。 在特定实施例中，每个节点有三个FIFO寄存器：输入FIFO寄存器，用于从外部源接收输入信息并将其提供给数据流存储器; 输出FIFO寄存器，用于从处理器向外部接收者提供输出信息; 以及内部FIFO寄存器，用于将来自处理器的信息提供回数据流存储器。 数据流存储器由四个通常被寻址的存储器组成。 参数存储器保存计算中使用的A和B参数; 操作码存储器保存指令; 目标存储器保存输出地址; 标签存储器包含每个参数的状态位。 一个状态位指示相应的参数是否在参数存储器中，并且一个状态，而是指示是否重新使用相应数据参数中存储的信息。 当所有必要信息已经存储在数据流存储器中时，标签存储器输出“火”信号（信号R VALID），并且因此当指令准备被触发到处理器时。

公开(公告)号：WO1998011483A1

公开(公告)日：1998-03-19

申请号：PCT/US1997015952

申请日：1997-09-08

Applicant: INTERNATIONAL COMPUTERS SCIENCE INSTITUTE

Inventor： INTERNATIONAL COMPUTERS SCIENCE INSTITUTE ,  ASANOVIC, Krste

IPC: G06F09/30

CPC classification number: G06F9/3001 ,  G06F9/30036 ,  G06F9/3877 ,  G06F9/3887 ,  G06F9/3897 ,  G06F15/8076

Abstract: A data processing system contains both a scalar processor (102) and a vector processor (104). The vector processor (104) contains a plurality of functional units (108), each of which contains a plurality of parallel pipelines, each of the pipelines contains a plurality of arithmetic and logic units (ALUs) connected via a plurality of data paths, such that data can be communicated between the ALUs during the execution of a vector instruction by the vector functional unit containing the pipeline. The operation performed by each of the cascaded ALUs and the paths through which data is to be communicated between the ALUs during the execution of a vector instruction can be controlled by configuration values held in a scalar register (105) named by the vector instruction. Through the use of this technique, multiple operations upon sets of vector data may be specified in a single short vector instruction, and further, the configuration of the pipelines can be determined dynamically in response to program input.

Abstract translation: 数据处理系统包含标量处理器（102）和矢量处理器（104）。 矢量处理器（104）包含多个功能单元（108），每个功能单元（108）包含多个并行流水线，每个流水线包含经由多个数据路径连接的多个算术和逻辑单元（ALU） 该数据可以在包含流水线的向量功能单元执行向量指令期间在ALU之间进行通信。 可以通过由矢量指令命名的标量寄存器（105）中保存的配置值来控制由级联ALU中的每一个执行的操作以及在执行向量指令期间在ALU之间传送数据的路径。 通过使用这种技术，可以在单个短向量指令中指定向量数据集合的多个操作，此外，可以响应于程序输入动态地确定管道的配置。

公开(公告)号：WO1998002797A1

公开(公告)日：1998-01-22

申请号：PCT/US1996011757

申请日：1996-07-16

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ADVANCED MICRO DEVICES, INC. ,  TRAN, Thang, M.

IPC: G06F09/30

CPC classification number: G06F9/382 ,  G06F9/30152 ,  G06F9/30167 ,  G06F9/3816

Abstract: A superscalar microprocessor is provided that includes a predecode unit configured to predecode variable byte-length instructions prior to their storage within an instruction cache. The predecode unit is configured to generate a plurality of predecode bits for each instruction byte. The plurality of predecode bits associated with each instruction byte are collectively referred to as a predecode tag. An instruction alignment unit then uses the predecode tags to dispatch the variable byte-length instructions simultaneously to a plurality of decode units which form fixed issue positions within the superscalar microprocessor. With the information conveyed by the functional bits, the decode units can detect the exact locations of the opcode, displacement, immediate, register, and scale-index bytes. Accordingly, no serial scan by the decode units through the instruction bytes is needed. In addition, the functional bits allow the decode units to calculate linear addresses (via adder circuits) expeditiously for use by other subunits within the superscalar microprocessor. Accordingly, relatively fast decoding may be attained, and high performance may be accommodated.

Abstract translation: 提供了一种超标量微处理器，其包括预定解码单元，其被配置为在可变字节长度指令存储在指令高速缓存之前预解码。 预解码单元被配置为为每个指令字节生成多个预解码位。 与每个指令字节相关联的多个预解码位被统称为预解码标签。 指令对准单元然后使用预解码标签将可变字节长度指令同时分配到在超标量微处理器内形成固定发布位置的多个解码单元。 通过功能位传送的信息，解码单元可以检测操作码，位移，立即数，寄存器和缩放索引字节的确切位置。 因此，不需要通过指令字节的解码单元的串行扫描。 此外，功能位允许解码单元计算线性地址（通过加法器电路），以便迅速地由超标量微处理器内的其他子单元使用。 因此，可以获得相对快速的解码，并且可以适应高性能。