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    EFFICIENT MULTICHANNEL FILTERING FOR CDMA MODEMS
    1.
    发明申请
    EFFICIENT MULTICHANNEL FILTERING FOR CDMA MODEMS 审中-公开
    CDMA模式的高效多通道滤波

    公开(公告)号：WO1997050173A1

    公开(公告)日：1997-12-31

    申请号：PCT/US1997010909

    申请日：1997-06-24

    Applicant: INTERDIGITAL TECHNOLOGY CORPORATION

    Inventor： INTERDIGITAL TECHNOLOGY CORPORATION ,  REGIS, Robert, T.

    IPC: H03H17/02

    CPC classification number: H04B1/7075 ,  H03H17/0226 ,  H03H17/06 ,  H04B1/707 ,  H04B1/70753 ,  H04B1/70755 ,  H04B1/70758 ,  H04B1/708 ,  H04B1/7093 ,  H04B2201/70702 ,  H04B2201/70707

    Abstract: An efficient, multichannel filter for CDMA modems permits multiple serial, digital bit streams to be filtered by digital signal processing techniques including sample weighting and summing functions. Each individual channel may have custom weighting coefficients or weighting coefficients common for all channels. If the weighting coefficients are by adaption, the same approach may be taken. The multichannel FIR filter is implemented with no multipliers and a reduction in the number of adders. To increase the speed of operation, the filter structure utilizes look-up tables storing the weighting coefficients. The invention can be embodied either as a field programmable gate array or an application specific integrated circuit. The use of look-up tables saves significant chip resources.

    Abstract translation: 用于CDMA调制解调器的有效的多通道滤波器允许通过包括采样加权和求和功能的数字信号处理技术对多个串行数字比特流进行滤波。 每个单独的通道可以具有对于所有通道共同的自定义加权系数或加权系数。 如果通过适应加权系数，则可以采用相同的方法。 多通道FIR滤波器实现没有乘法器和减少加法器的数量。 为了提高操作速度，滤波器结构利用存储加权系数的查找表。 本发明可以被实现为现场可编程门阵列或专用集成电路。 查找表的使用节省了大量的芯片资源。

    A METHOD OF CONTROLLING INITIAL POWER RAMP-UP IN CDMA SYSTEMS BY USING SHORT CODES
    3.
    发明申请
    A METHOD OF CONTROLLING INITIAL POWER RAMP-UP IN CDMA SYSTEMS BY USING SHORT CODES 审中-公开
    通过使用短码控制CDMA系统中的初始功率放大的方法

    公开(公告)号：WO1997050194A2

    公开(公告)日：1997-12-31

    申请号：PCT/US1997010754

    申请日：1997-06-23

    Applicant: INTERDIGITAL TECHNOLOGY CORPORATION

    Inventor： INTERDIGITAL TECHNOLOGY CORPORATION ,  OZLUTURK, Fatih, M. ,  LOMP, Gary, R. ,  HAIM, John, W.

    IPC: H04B07/005

    CPC classification number: H04W52/60 ,  H04B1/707 ,  H04B1/7075 ,  H04B1/70753 ,  H04B1/70755 ,  H04B1/70758 ,  H04B1/7077 ,  H04B1/708 ,  H04B2201/70701 ,  H04B2201/70702 ,  H04B2201/70703 ,  H04B2201/70707 ,  H04B2201/7071 ,  H04W52/36 ,  H04W52/362 ,  H04W52/367 ,  H04W52/50

    Abstract: A system and method of controlling transmission power during the establishment of a channel in a CDMA communication system utilize the transmission of a short code from a subscriber unit to a base station during initial power ramp-up. The short code is a sequence for detection by the base station which has a much shorter period than a conventional spreading code. The ramp-up starts from a power level that is guaranteed to be lower than the required power level for detection by the base station. The subscriber unit quickly increases transmission power while repeatedly transmitting the short code until the signal is detected by the base station. Once the base station detects the short code, it sends an indication to the subscriber unit to cease increasing transmission power. The use of short codes limits power overshoot and interference to other subscriber stations and permits the base station to quickly synchronize to the spreading code used by the subscriber unit.

    Abstract translation: 在CDMA通信系统建立信道期间控制发射功率的系统和方法利用在初始功率提升期间从用户单元向基站传输短码。 短码是用于基站检测的序列，其具有比常规扩展码短得多的周期。 斜坡上升从功率电平开始，该功率电平保证低于基站检测所需的功率电平。 用户单元快速增加发射功率，同时重复发送短码直到基站检测到信号。 一旦基站检测到短码，它就向用户单元发送指示，以停止增加发射功率。 使用短码限制了对其他用户站的功率过冲和干扰，并允许基站快速同步到用户单元使用的扩展码。

    SPREAD SPECTRUM INTERFERENCE CANCELER SYSTEM AND METHOD
    5.
    发明申请
    SPREAD SPECTRUM INTERFERENCE CANCELER SYSTEM AND METHOD 审中-公开
    传播频谱干扰消除系统和方法

    公开(公告)号：WO1996003819A1

    公开(公告)日：1996-02-08

    申请号：PCT/US1995009652

    申请日：1995-07-05

    Applicant: INTERDIGITAL TECHNOLOGY CORPORATION

    Inventor： INTERDIGITAL TECHNOLOGY CORPORATION ,  SCHILLING, Donald, L. ,  KOWALSKI, John ,  MOSHAVI, Shimon

    IPC: H04J13/02

    CPC classification number: H04B1/71075 ,  H04B1/709 ,  H04B1/7093

    Abstract: A spread-spectrum CDMA interference canceler for reducing interference in a DS/CDMA receiver having N chip-code channels. The interference canceler includes a plurality of correlators (54, 64, 74), a plurality of spread-spectrum-processing circuits (55, 65, 75), subtracting circuits (150), and channel correlators (146). Using a plurality of chip-code signals generated from chip codeword signal generators (52, 62, 72), the correlators (54, 64, 74) despreads the spread-spectrum CDMA signal as a plurality of despread signals. The plurality of spread-spectrum-processing circuits (55, 65, 75) uses a timed version of the plurality of chip-code signals generated from the delay devices (53, 63, 73), for spread-spectrum processing the plurality of despread signals. For recovering a code channel using an i chip-code-signal, the subtracting circuits (150) subtracts from the spread-spectrum CDMA signal, each of the N-1 spread-spectrum-processed-despread signals thereby generating a subtracted signal. The channel-correlator (146) despreads the subtracted signal.

    Abstract translation: 扩频CDMA干扰消除器，用于减少具有N个码片信道的DS / CDMA接收机中的干扰。 干扰消除器包括多个相关器（54,64,74），多个扩频处理电路（55,65,75），减法电路（150）和信道相关器（146）。 使用从芯片码字信号发生器（52,62,72）生成的多个芯片码信号，相关器（54,64,74）将扩频CDMA信号解扩展为多个解扩信号。 多个扩频处理电路（55,65,75）使用从延迟装置（53,63,73）生成的多个码片信号的定时版本，用于扩频处理多个解扩频 信号。 为了使用第i个码片码信号恢复代码信道，减法电路（150）从扩频CDMA信号中减去N-1个扩频处理的解扩信号，从而产生一个减法 信号。 信道相关器（146）对相减信号进行解扩。

    SPREAD-SPECTRUM CHANGEABLE BASE STATION
    6.
    发明申请
    SPREAD-SPECTRUM CHANGEABLE BASE STATION 审中-公开
    可扩展基站可扩展基站

    公开(公告)号：WO1996001013A1

    公开(公告)日：1996-01-11

    申请号：PCT/US1995008561

    申请日：1995-06-16

    Applicant: INTERDIGITAL TECHNOLOGY CORPORATION

    Inventor： INTERDIGITAL TECHNOLOGY CORPORATION ,  SCHILLING, Donald, L.

    IPC: H04B07/216

    CPC classification number: H04W88/06 ,  H04B1/707 ,  H04B1/7093 ,  H04M3/56 ,  H04M2207/18 ,  H04W72/005 ,  H04W84/20 ,  H04W88/08

    Abstract: A conference calling spread-spectrum communications system and method using a plurality of spread-spectrum units, any one of which may serve as the base station and where the base station may be changed upon demand. Each spread-sprectrum unit includes a base subunit (11-21), a remote subunit (40), and a command subunit (41-44). An operator may initiate from the command subunit (41-44), a command signal to activate the base subunit (11-21). Accordingly, upon initiating the command signal, the command signal is broadcast to the plurality of spread-spectrum units. At the respective remote subunit (40), in each of the spread-spectrum units, the command signal is received, and in response to receiving the command signal, the remote subunit (40) is activated.

    Abstract translation: 一种使用多个扩频单元的会议呼叫扩频通信系统和方法，其中任一个可以用作基站，并且可以在需要时更改基站。 每个扩展单元包括基本子单元（11-21），远程子单元（40）和命令子单元（41-44）。 操作员可以从命令子单元（41-44）发起一个激活基本子单元（11-21）的命令信号。 因此，在启动命令信号时，将指令信号广播到多个扩频单元。 在相应的远程子单元（40）处，在每个扩频单元中接收命令信号，并且响应于接收到命令信号，远程子单元（40）被激活。

    METHOD AND APPARATUS FOR COMPRESSING AND TRANSMITTING HIGH SPEED DATA
    7.
    发明申请
    METHOD AND APPARATUS FOR COMPRESSING AND TRANSMITTING HIGH SPEED DATA 审中-公开
    压缩和传输高速数据的方法和装置

    公开(公告)号：WO1998020696A2

    公开(公告)日：1998-05-14

    申请号：PCT/US1997020092

    申请日：1997-11-04

    Applicant: INTERDIGITAL TECHNOLOGY CORPORATION

    Inventor： INTERDIGITAL TECHNOLOGY CORPORATION ,  KURTZ, Scott, David

    IPC: H04Q07/38

    CPC classification number: H04W72/0446 ,  H03M7/30 ,  H04B14/046 ,  H04L1/0041 ,  H04L1/0071 ,  H04L5/06 ,  H04L25/4927 ,  H04W24/00 ,  H04W28/06 ,  H04W72/04 ,  H04W72/0453 ,  H04W74/04 ,  H04W88/08

    Abstract: Two-related voiceband compression techniques are employed in order to enable an RF telecommunications system to accommodate data signals of high speed voiceband modems and FAX machines. A High Speed Codec enables the telecommunications system to pass voiceband modem and FAX transmissions at up to 9.6 kb/s. An Ultra-High Speed Codec supports voiceband modem and FAX transmissions up to 14.4 kb/s. The High Speed Codec operates using three 16-phase RF slots or four 8-phase RF slots, and the Ultra-High Speed Codec operates using four 16-phase RF slots. Because these codecs transmit information over several RF slots which can be contiguous, the slots within RF communication channels are dynamically allocated. The Dynamic Timeslot/Bandwidth Allocation feature detects and monitors the data transmission and forms a data channel from the necessary number of slots.

    Abstract translation: 为了使RF电信系统能够适应高速语音频带调制解调器和传真机的数据信号，采用了两种相关的话音频带压缩技术。 高速编解码器使得电信系统能够以高达9.6kb / s的速率传输语音频带调制解调器和传真传输。 超高速编解码器支持高达14.4 kb / s的语音频带调制解调器和传真传输。 高速编解码器使用三个16相RF插槽或四个8相RF插槽进行操作，超高速编解码器使用四个16相RF插槽进行操作。 因为这些编解码器通过可以是连续的几个RF时隙发送信息，所以RF通信信道中的时隙被动态分配。 动态时隙/带宽分配功能检测和监视数据传输，并从必要数量的时隙形成数据通道。

    PARALLEL PACKETIZED INTERMODULE ARBITRATED HIGH SPEED CONTROL AND DATA BUS
    9.
    发明申请
    PARALLEL PACKETIZED INTERMODULE ARBITRATED HIGH SPEED CONTROL AND DATA BUS 审中-公开
    并行封装的INTERMODULE仲裁高速控制和数据总线

    公开(公告)号：WO1997050039A1

    公开(公告)日：1997-12-31

    申请号：PCT/US1997011607

    申请日：1997-06-27

    Applicant: INTERDIGITAL TECHNOLOGY CORPORATION

    Inventor： INTERDIGITAL TECHNOLOGY CORPORATION ,  REGIS, Robert, T.

    IPC: G06F13/374

    CPC classification number: H04B1/7075 ,  G06F13/374 ,  G06F13/376 ,  H04B1/70753 ,  H04B1/70755 ,  H04B1/70758 ,  H04B1/708 ,  H04B2201/70702

    Abstract: A parallel packetized intermodule arbitrated high speed control data bus system which allows high speed communications between microprocessor modules in a more complex digital processing environment. The system features a simplified hardware architecture featuring fast FIFO queuing operating at 12.5 MHz, TTL CMOS compatible level clocking signals, single bus master arbitration, synchronous clocking, DMA, and unique module addressing for multiprocessor systems. The system includes a parallel data bus with sharing bus masters residing on each processing module decreeing the commzunication and data transfer protocols. Bus arbitration is performed over a dedicated serial arbitration line and each requesting module competes for access to the parallel data bus by placing the address of the receiving module on the arbitration line and monitoring the arbitration line for collisions.

    Abstract translation: 并行分组式串联仲裁高速控制数据总线系统，允许在更复杂的数字处理环境中的微处理器模块之间进行高速通信。 该系统具有简化的硬件体系结构，具有12.5 MHz快速FIFO排队，TTL CMOS兼容级别时钟信号，单总线主仲裁，同步时钟，DMA和多处理器系统的独特模块寻址。 该系统包括一个并行数据总线，共享总线主机驻留在每个处理模块上，确定通信和数据传输协议。 总线仲裁通过专用串行仲裁线执行，并且每个请求模块通过将接收模块的地址放置在仲裁线路上并监视仲裁线路进行冲突来竞争对并行数据总线的访问。

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