中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

20 records (took 0.008 seconds)

    PARALLEL PACKETIZED INTERMODULE ARBITRATED HIGH SPEED CONTROL AND DATA BUS
    1.
    发明申请
    PARALLEL PACKETIZED INTERMODULE ARBITRATED HIGH SPEED CONTROL AND DATA BUS 审中-公开
    并行封装的INTERMODULE仲裁高速控制和数据总线

    公开(公告)号：WO1997050039A1

    公开(公告)日：1997-12-31

    申请号：PCT/US1997011607

    申请日：1997-06-27

    Applicant: INTERDIGITAL TECHNOLOGY CORPORATION

    Inventor： INTERDIGITAL TECHNOLOGY CORPORATION ,  REGIS, Robert, T.

    IPC: G06F13/374

    CPC classification number: H04B1/7075 ,  G06F13/374 ,  G06F13/376 ,  H04B1/70753 ,  H04B1/70755 ,  H04B1/70758 ,  H04B1/708 ,  H04B2201/70702

    Abstract: A parallel packetized intermodule arbitrated high speed control data bus system which allows high speed communications between microprocessor modules in a more complex digital processing environment. The system features a simplified hardware architecture featuring fast FIFO queuing operating at 12.5 MHz, TTL CMOS compatible level clocking signals, single bus master arbitration, synchronous clocking, DMA, and unique module addressing for multiprocessor systems. The system includes a parallel data bus with sharing bus masters residing on each processing module decreeing the commzunication and data transfer protocols. Bus arbitration is performed over a dedicated serial arbitration line and each requesting module competes for access to the parallel data bus by placing the address of the receiving module on the arbitration line and monitoring the arbitration line for collisions.

    Abstract translation: 并行分组式串联仲裁高速控制数据总线系统，允许在更复杂的数字处理环境中的微处理器模块之间进行高速通信。 该系统具有简化的硬件体系结构，具有12.5 MHz快速FIFO排队，TTL CMOS兼容级别时钟信号，单总线主仲裁，同步时钟，DMA和多处理器系统的独特模块寻址。 该系统包括一个并行数据总线，共享总线主机驻留在每个处理模块上，确定通信和数据传输协议。 总线仲裁通过专用串行仲裁线执行，并且每个请求模块通过将接收模块的地址放置在仲裁线路上并监视仲裁线路进行冲突来竞争对并行数据总线的访问。

    CONTROL ARRANGEMENT BASED ON CAN-BUS TECHNOLOGY
    3.
    发明申请
    CONTROL ARRANGEMENT BASED ON CAN-BUS TECHNOLOGY 审中-公开
    基于CAN总线技术的控制装置

    公开(公告)号：WO02054163A1

    公开(公告)日：2002-07-11

    申请号：PCT/SE2002/000002

    申请日：2002-01-02

    IPC: H04L12/413 ,  G05B19/042 ,  G06F13/374

    CPC classification number: H04L12/4135 ,  G05B2219/25032 ,  G05B2219/25331 ,  G05B2219/31136 ,  H04L2012/40215 ,  Y02P90/18

    Abstract: The present invention relates to an arrangement for controlling a plurality of controllable devices (55a, 55b) connected to at least one common bus (24). The arrangement comprises at least one input member (21) and at least one output member (22) interconnected through said common bus (24), each input and output member having at least one input terminal (35) and at least one output terminal (45), respectively. Each input/output terminal has a unique identity, said input member (21) being arranged to receive a control signal from at least one control arrangement (51a-51c) connected to said at least one input terminal (35) of said input member. The control signal generates an action signal comprising an address corresponding to a unique identity of an output terminal of said output member (22) connected to at least one of said controllable devices (55a, 55b). The action signal is provided on said common bus by said input member to be received by said output member.

    Abstract translation: 本发明涉及一种用于控制连接到至少一个公共总线（24）的多个可控设备（55a，55b）的装置。 该装置包括至少一个输入构件（21）和通过所述公共总线（24）互连的至少一个输出构件（22），每个输入和输出构件具有至少一个输入端子（35）和至少一个输出端子 45）。 每个输入/输出端子具有唯一的标识，所述输入构件（21）被布置成从连接到所述输入构件的所述至少一个输入端子（35）的至少一个控制装置（51a-51c）接收控制信号。 控制信号产生动作信号，该动作信号包括与所述可控装置（55a，55b）中的至少一个连接的所述输出部件（22）的输出端子的唯一标识对应的地址。 所述动作信号由所述输入部件设置在所述公共总线上，以由所述输出部件接收。

    PROVIDING PRIORITY INDICATORS FOR NVME DATA COMMUNICATION STREAMS
    7.
    发明申请
    PROVIDING PRIORITY INDICATORS FOR NVME DATA COMMUNICATION STREAMS 审中-公开

    公开(公告)号：WO2022271213A1

    公开(公告)日：2022-12-29

    申请号：PCT/US2022/017930

    申请日：2022-02-25

    Applicant: WESTERN DIGITAL TECHNOLOGIES, INC.

    Inventor： SURIANARAYANAN, Ravishankar

    IPC: G06F9/48 ,  G06F9/38 ,  G06F9/50 ,  G06F13/42 ,  G06F13/374 ,  G06F3/061 ,  G06F3/0631 ,  G06F3/0655 ,  G06F3/0679 ,  H04L67/141

    Abstract: Systems and methods described herein provide for determining priority levels within one or more data streams established between a host computing device and a storage device. Data streams that have been assigned a sufficiently high priority may be provided additional processing resources available within the storage device. These additional processing resources may include an increased number of write buffers, superblocks, and access to other ancillary resources that facilitate an increased level of performance compared to data streams not provided additional processing resources. The assignment of priority to the data streams can occur through the use of one or more priority identifiers. Many types and scales of priority identifiers may be used. The establishing of this system of priority identifiers can occur by the storage device notifying the hose of the accepted priority identifier usage. In other embodiments, the storage device may come preconfigured with a priority indication system and scale.

    METHOD FOR ALLOCATING ADDRESSES AND CORRESPONDING UNITS
    8.
    发明申请
    METHOD FOR ALLOCATING ADDRESSES AND CORRESPONDING UNITS 审中-公开

    公开(公告)号：WO2020147932A1

    公开(公告)日：2020-07-23

    申请号：PCT/EP2019/050939

    申请日：2019-01-15

    Applicant: HELDEIS, Christoph

    Inventor： HELDEIS, Christoph ,  HACKE, Tilo

    IPC: G06F13/37 ,  G06F13/42 ,  G06F13/16 ,  G06F13/374 ,  H04L12/40 ,  H04L12/417 ,  H05B37/02 ,  H04L29/12

    Abstract: A Method for allocating addresses to electronic units (SLC) is described, comprising: - providing a first electronic unit (SLC1) and a second electronic unit (SLC1), - generating a wirelessly transmitted signal for detecting or generating one signal or several signals for detection on a chain (4) of electronic elements (R1 to Rn), - within or for the first unit (SLC1), detecting a first value or the transmission time of the wirelessly transmitted signal for detection or detecting a first value (S14, S28) or a first transmission time on a first position (R1) of the chain (4), - within or for the second unit (SLC2), detecting a second value or the transmission time of the wirelessly transmitted signal for detection or detecting a second value or a second transmission time on a second position (R2) of the chain (4) that is different from the first position (R1), - converting the first value or the transmission time detected within or for the first unit (SLC1) to a first address for the first unit (SLC1), and - converting the second value or the transmission time detected within or for the second unit (SLC2) to a second address for the second unit (SLC1).

    METHOD FOR IMPLICIT ADDRESSING OF ELECTRONIC UNITS AND CORRESPONDING UNITS
    9.
    发明申请
    METHOD FOR IMPLICIT ADDRESSING OF ELECTRONIC UNITS AND CORRESPONDING UNITS 审中-公开

    公开(公告)号：WO2020147931A1

    公开(公告)日：2020-07-23

    申请号：PCT/EP2019/050937

    申请日：2019-01-15

    Applicant: HELDEIS, Christoph

    Inventor： HELDEIS, Christoph ,  HACKE, Tilo

    IPC: G06F13/42 ,  G06F13/37 ,  G06F13/16 ,  G06F13/374 ,  H04L12/40 ,  H04L12/417 ,  H05B37/02 ,  H04L29/12

    Abstract: A method for implicit addressing is described that comprises: - providing (S504) within a first unit (SLC1) and within a second unit (SLC2) respectively a counter unit, a comparison unit and a storing unit for the storage of an identifier, - allocating (S506) a first identifier to the first unit (SLC1), - allocating (S506) a second identifier that is different from the first identifier to the second unit (SLC2), - setting (S508) the same counter value in the counter units of both units (SLC1, SLC2), - after setting (S508) the counter values comparing (S520) the counter value in the first unit (SLC1) to the first identifier and comparing (S530) the counter value in the second unit (SLC2) to the second identifier, - based on equality of the comparison in the first unit (SLC1) sending (S522) of first data from the first unit or (S522) assigning of first data to the first unit (SLC1), based on inequality (S531) of the comparison in the second unit (SLC2) no sending of data or assigning of data to the second unit (SLC2), and - counting up (S526, S536) or down the counter value in both units (SLC1, SLC2).

Patent Agency Ranking