公开(公告)号：WO2021049990A1

公开(公告)日：2021-03-18

申请号：PCT/SE2020/050823

申请日：2020-08-27

Applicant: K.EKLUND INNOVATION

Inventor： EKLUND, Klas-Håkan ,  VESTLING, Lars

IPC: H01L29/06 ,  H01L27/085 ,  H01L29/10 ,  H01L29/417 ,  H01L29/47 ,  H01L29/739 ,  H01L29/808 ,  H01L29/78

Abstract: A semiconductor device, comprising an insulated gate field effect transistor (1) connected in series with a field effect transistor (2), FET, wherein the FET (2) comprises several parallel conductive layers (n1-n5, p1-p4), and wherein a substrate (11) of first conductivity type is arranged as the basis for the semi- conductor device, stretching under both transistors (1, 2), a first layer of a second conductivity type (n1) is arranged stretching over the substrate (11), wherein on top of this first layer (n1) are arranged several conductive layers with channels formed by several of the first conductivity type doped epitaxial layers (n2-n4) with layers of a first conductivity type (p1-p4) on both sides, wherein the uppermost layer (p5) of the device is preferably substantially thicker than the directly underlying several parallel conductive layers (p1-p4, n1-n4), and that the field effect transistor (2), JFET, is isolated with deep poly trenches of second conductivity type, DNPT, (22) on the source side of the JFET, and the insulated gate field effect transistor (1) is isolated with deep poly trenches of the first conductivity type, DPPT, (22, 23) on both sides, and a further isolated region (5) comprising logics and analogue control functions is isolated with deep poly trenches of the first conductivity type, DPPT, (23, 24) on both sides.

公开(公告)号：WO2012121650A1

公开(公告)日：2012-09-13

申请号：PCT/SE2012/050234

申请日：2012-03-01

Applicant: K.EKLUND INNOVATION ,  EKLUND, Klas-Håkan ,  VESTLING, Lars

Inventor： EKLUND, Klas-Håkan ,  VESTLING, Lars

IPC: H01L29/808

CPC classification number: H01L27/0617 ,  H01L29/0634 ,  H01L29/7835

Abstract: A semiconductor device comprising a substrate (22), a body region (25) adjoining the surface (24) of the substrate (22), a source contact region (26) within the body region (25), a drain contact region (27) adjoining the surface (24) of the substrate (22) and being separated from the body region (25), a dual JFET gate region (33) located between the body region (25) and the drain contact region (27),and a lateral JFET channel region (36) adjoining the surface (24) of the substrate (22) and which is located between the body region (25) and the drain contact region (27), wherein a vertical JFET gate region (32) is arranged essentially enclosed by the body region (25),a vertical JFET channel region (34) being arranged between the vertical JFET gate region (32) essentially enclosed by the body region (25) and said dual JFET gate region (33), a reduced drain resistance region (35) being arranged between said dual JFET gate region (33) and the drain contact region (27), and a buried pocket (23) being located under part of said body region (25), under said dual JFET gate region (33) and under said vertical JFET channel and reduced drain resistance regions (34, 35).

Abstract translation: 一种半导体器件，包括衬底（22），与衬底（22）的表面（24）相邻的体区（25），体区（25）内的源极接触区（26），漏极接触区（27） ）与衬底（22）的表面（24）相邻并且与身体区域（25）分离;位于身体区域（25）和漏极接触区域（27）之间的双JFET栅极区域（33），以及 位于衬底（22）的表面（24）之间并且位于主体区域（25）和漏极接触区域（27）之间的横向JFET沟道区域（36），其中垂直JFET栅极区域（32）是 被布置成基本上由所述体区域（25）包围;垂直JFET沟道区域（34），布置在基本上由所述体区域（25）和所述双JFET栅极区域（33）封闭的所述垂直JFET栅极区域（32）之间， 布置在所述双JFET栅极区域（33）和漏极接触区域（27）之间的减小的漏极阻抗区域（35） 23）位于所述体区（25）的下方，位于所述双JFET栅极区域（33）下方，并位于所述垂直JFET沟道和降低的漏极阻抗区域（34,35）之下。