公开(公告)号：WO2021049990A1

公开(公告)日：2021-03-18

申请号：PCT/SE2020/050823

申请日：2020-08-27

Applicant: K.EKLUND INNOVATION

Inventor： EKLUND, Klas-Håkan ,  VESTLING, Lars

IPC: H01L29/06 ,  H01L27/085 ,  H01L29/10 ,  H01L29/417 ,  H01L29/47 ,  H01L29/739 ,  H01L29/808 ,  H01L29/78

Abstract: A semiconductor device, comprising an insulated gate field effect transistor (1) connected in series with a field effect transistor (2), FET, wherein the FET (2) comprises several parallel conductive layers (n1-n5, p1-p4), and wherein a substrate (11) of first conductivity type is arranged as the basis for the semi- conductor device, stretching under both transistors (1, 2), a first layer of a second conductivity type (n1) is arranged stretching over the substrate (11), wherein on top of this first layer (n1) are arranged several conductive layers with channels formed by several of the first conductivity type doped epitaxial layers (n2-n4) with layers of a first conductivity type (p1-p4) on both sides, wherein the uppermost layer (p5) of the device is preferably substantially thicker than the directly underlying several parallel conductive layers (p1-p4, n1-n4), and that the field effect transistor (2), JFET, is isolated with deep poly trenches of second conductivity type, DNPT, (22) on the source side of the JFET, and the insulated gate field effect transistor (1) is isolated with deep poly trenches of the first conductivity type, DPPT, (22, 23) on both sides, and a further isolated region (5) comprising logics and analogue control functions is isolated with deep poly trenches of the first conductivity type, DPPT, (23, 24) on both sides.

公开(公告)号：WO2012121650A1

公开(公告)日：2012-09-13

申请号：PCT/SE2012/050234

申请日：2012-03-01

Applicant: K.EKLUND INNOVATION ,  EKLUND, Klas-Håkan ,  VESTLING, Lars

Inventor： EKLUND, Klas-Håkan ,  VESTLING, Lars

IPC: H01L29/808

CPC classification number: H01L27/0617 ,  H01L29/0634 ,  H01L29/7835

Abstract: A semiconductor device comprising a substrate (22), a body region (25) adjoining the surface (24) of the substrate (22), a source contact region (26) within the body region (25), a drain contact region (27) adjoining the surface (24) of the substrate (22) and being separated from the body region (25), a dual JFET gate region (33) located between the body region (25) and the drain contact region (27),and a lateral JFET channel region (36) adjoining the surface (24) of the substrate (22) and which is located between the body region (25) and the drain contact region (27), wherein a vertical JFET gate region (32) is arranged essentially enclosed by the body region (25),a vertical JFET channel region (34) being arranged between the vertical JFET gate region (32) essentially enclosed by the body region (25) and said dual JFET gate region (33), a reduced drain resistance region (35) being arranged between said dual JFET gate region (33) and the drain contact region (27), and a buried pocket (23) being located under part of said body region (25), under said dual JFET gate region (33) and under said vertical JFET channel and reduced drain resistance regions (34, 35).

Abstract translation: 一种半导体器件，包括衬底（22），与衬底（22）的表面（24）相邻的体区（25），体区（25）内的源极接触区（26），漏极接触区（27） ）与衬底（22）的表面（24）相邻并且与身体区域（25）分离;位于身体区域（25）和漏极接触区域（27）之间的双JFET栅极区域（33），以及 位于衬底（22）的表面（24）之间并且位于主体区域（25）和漏极接触区域（27）之间的横向JFET沟道区域（36），其中垂直JFET栅极区域（32）是 被布置成基本上由所述体区域（25）包围;垂直JFET沟道区域（34），布置在基本上由所述体区域（25）和所述双JFET栅极区域（33）封闭的所述垂直JFET栅极区域（32）之间， 布置在所述双JFET栅极区域（33）和漏极接触区域（27）之间的减小的漏极阻抗区域（35） 23）位于所述体区（25）的下方，位于所述双JFET栅极区域（33）下方，并位于所述垂直JFET沟道和降低的漏极阻抗区域（34,35）之下。

公开(公告)号：WO2014185852A1

公开(公告)日：2014-11-20

申请号：PCT/SE2014/050577

申请日：2014-05-12

Applicant: K.EKLUND INNOVATION

Inventor： EKLUND, Klas-Håkan

IPC: H01L29/73 ,  H01L29/66

CPC classification number: H01L29/7393 ,  H01L23/535 ,  H01L27/0623 ,  H01L29/0649 ,  H01L29/0808 ,  H01L29/0821 ,  H01L29/0847 ,  H01L29/1008 ,  H01L29/1033 ,  H01L29/1095 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The present invention provides a lateral IGBT transistor comprising a bipolar transistor and an IGFET. The lateral IGBT comprises a low resistive connection between the drain of the IGFET and the base of the bipolar transistor, and an isolating layer arranged between the IGFET and the bipolar transistor. The novel structure provides a device which is immune to latch and gives high gain and reliability. The structure can be realized with standard CMOS technology available at foundries.

Abstract translation: 本发明提供一种包括双极晶体管和IGFET的横向IGBT晶体管。 横向IGBT包括IGFET的漏极和双极晶体管的基极之间的低电阻连接，以及布置在IGFET和双极晶体管之间的隔离层。 该新颖结构提供了一种对锁存器免疫并具有高增益和可靠性的装置。 该结构可以通过铸造厂提供的标准CMOS技术实现。

公开(公告)号：WO2014204394A1

公开(公告)日：2014-12-24

申请号：PCT/SE2014/050743

申请日：2014-06-17

Applicant: K.EKLUND INNOVATION

Inventor： EKLUND, Klas-Håkan ,  ZHANG, Shili ,  SMITH, Ulf ,  NORSTRÖM, Hans Erik

IPC: G01N27/414 ,  H01L29/732 ,  H01L29/739

CPC classification number: G01N27/4145 ,  G01N27/414 ,  H01L27/0623

Abstract: According to a first aspect of the present innovation there is provided a semiconductor based integrated sensor device comprising: a lateral insulating-gate field effect transistor (MOSFET) connected in series to the base of a vertical bipolar junction transistor (BJT) wherein the drain-drift-region of said MOSFET is part of the base-region of the BJT within the semiconductor substrate thus making electrical contact to the base of the BJT and the distance of the drain-drift-region of the MOSFET to the emitter of the BJT exceeds the vertical distance between the emitter and any buried layer, serving as collector, and the breakdown voltage of the device being determined by the BVCEO of the vertical BJT.

Abstract translation: 根据本发明的第一方面，提供了一种基于半导体的集成传感器装置，包括：与垂直双极结型晶体管（BJT）的基极串联连接的横向绝缘栅场效应晶体管（MOSFET），其中， 所述MOSFET的漂移区域是半导体衬底内的BJT的基极区域的一部分，从而与BJT的基极电接触，并且MOSFET的漏 - 漂移区域距离BJT的发射极的距离超过 用作集电极的发射极和任何掩埋层之间的垂直距离，以及器件的击穿电压由垂直BJT的BVCEO确定。