公开(公告)号：WO2021102382A1

公开(公告)日：2021-05-27

申请号：PCT/US2020/061685

申请日：2020-11-20

Applicant: MENTIUM TECHNOLOGIES INC.

Inventor： BAYAT, Farnood, Merrikh

IPC: G06F7/42 ,  G06F7/485 ,  G06F7/505

Abstract: Operations may include obtaining input data and separating the input data into a first subset of input data and a second subset of input data, the first subset of input data including positive input data and the second subset of input data including negative input data. The operations may include performing positive computations on the first subset of input data to determine one or more first results and performing negative computations on the second subset of input data to determine one or more second results. The operations may include aggregating the one or more first results and the one or more second results to determine a solution based on the aggregating. The operations may include executing an application using a machine learning model or a deep neural network based on the determined solution.

公开(公告)号：WO2021195104A1

公开(公告)日：2021-09-30

申请号：PCT/US2021/023718

申请日：2021-03-23

Applicant: MENTIUM TECHNOLOGIES INC.

Inventor： BAYAT, Farnood, Merrikh

IPC: G06N3/04 ,  G06N3/08 ,  G06N99/00 ,  G06N3/0635

Abstract: A hybrid accelerator architecture consisting of digital accelerators and in-memory computing accelerators. A processor managing the data movement may determine whether input data is more efficiently processed by the digital accelerators or the in-memory computing accelerators. Based on the determined efficiencies, input data may be distributed for processing to the accelerator determined to be more efficient.

公开(公告)号：WO2021011923A1

公开(公告)日：2021-01-21

申请号：PCT/US2020/042666

申请日：2020-07-17

Applicant: MENTIUM TECHNOLOGIES INC.

Inventor： BAYAT, Farnood, Merrikh ,  SULIMA, Jaroslaw ,  PREZIOSO, Mirko

IPC: G11C7/04 ,  G11C7/12 ,  G11C11/417

Abstract: A memory system having a temperature effect compensation mechanism is provided. The memory system memory cells in an array having rows of memory cells arranged horizontally and columns arranged vertically. The memory cells have an operating temperature range. The memory system also includes a temperature-dependent biasing circuit that reduces a biasing voltage to the memory cells when the temperature of the array is at or near an upper end of the operating temperature range and increases the biasing voltage when the temperature of the array is at or near a lower end of the operating temperature range. Also provided are comparators for submicron processes, analog-to-digital converters for non-volatile memory arrays used for in-memory computation with floating bitlines, and methods and structures for programming non-volatile memory arrays with automatic programming pulse amplitude adjustment using current-limiting circuits.