公开(公告)号：WO2004098065A1

公开(公告)日：2004-11-11

申请号：PCT/US2003/017405

申请日：2003-06-02

Applicant: ESS TECHNOLOGY, INC. ,  MALLINSON, Andrew, Martin

Inventor： MALLINSON, Andrew, Martin

IPC: H03M7/00

CPC classification number: H03M7/3004 ,  H03H17/0248 ,  H03M7/3028 ,  H03M7/3042

Abstract: The invention is directed to a bi-quad filter circuit (100) configured with sigma-delta devices (108, 110, 118) that operate as binary rate multipliers (BRMs) (200). Unlike conventional bi-quad filter circuits (100), the invention provides a bi-quad filter (100) configured with a single-bit BRM (200). In another embodiment, the invention further provides a bi-quad filter (100) configured with multiple-bit BRMs.

Abstract translation: 本发明涉及一种双二进制滤波器电路（100），其配置为以二进制比率乘法器（BRM）（200）运行的Σ-Δ器件（108,110,118）。 与传统的双二进制滤波器电路（100）不同，本发明提供一种配置有单位BRM（200）的双四滤波器（100）。 在另一个实施例中，本发明还提供了一种配置有多位BRM的双四边形滤波器（100）。

公开(公告)号：WO2004095704A2

公开(公告)日：2004-11-04

申请号：PCT/US2003/038911

申请日：2003-12-08

Applicant: ESS TECHNOLOGY, INC. ,  MALLINSON, Andrew, Martin

Inventor： MALLINSON, Andrew, Martin

IPC: H03L

CPC classification number: H03M7/3015 ,  H03M3/39 ,  H03M3/50 ,  H03M7/3028

Abstract: A sigma delta circuit is provided having a sigma delta modulator configured to operate according to a first clock signal and a quantizer connected to the sigma delta modulator, where the quantizer is configured to operate according to a second clock signal. In operation, if a small amplitude signal is received by the sigma delta circuit, the circuit is configured to operate at a fixed output frequency. When a large amplitude signal is received, the circuit is configured to adjust to a different frequency to accommodate the larger signal. The second clock signal may be a variable clock signal, where the quantizer operates according to a variable clock signal in order to adjust to different input signals.

Abstract translation: 提供了一个Σ-Δ电路，其具有被配置为根据第一时钟信号和连接到Σ-Δ调制器的量化器进行操作的Σ-Δ调制器，其中量化器被配置为根据第二时钟信号进行操作。 在操作中，如果Σ-Δ电路接收到小振幅信号，则电路被配置为以固定的输出频率工作。 当接收到大振幅信号时，电路被配置成调节到不同的频率以适应较大的信号。 第二时钟信号可以是可变时钟信号，其中量化器根据可变时钟信号进行操作，以便调整到不同的输入信号。

公开(公告)号：WO2004088847A2

公开(公告)日：2004-10-14

申请号：PCT/US2004009348

申请日：2004-03-26

Applicant: ESS TECHNOLOGY INC ,  MALLINSON ANDREW MARTIN

Inventor： MALLINSON ANDREW MARTIN

IPC: H03M1/06 ,  H03M1/08 ,  H03M1/66 ,  H03M

CPC classification number: H03M1/0663 ,  H03M1/0614 ,  H03M1/0682 ,  H03M1/66

Abstract: A high quality DAC is provided for a lower cost (including the layout size of the circuit on an audio chip) of high end DACs. The DAC includes a first circuit configured to remove even harmonics from a sigma delta circuit, and a second circuit configured to remove odd harmonics.

Abstract translation: 高端DAC的低成本（包括音频芯片的电路布局尺寸）提供了高质量的DAC。 DAC包括被配置为从Σ-Δ电路去除偶次谐波的第一电路和被配置为去除奇数谐波的第二电路。

公开(公告)号：WO2004088843A2

公开(公告)日：2004-10-14

申请号：PCT/US2004009350

申请日：2004-03-26

Applicant: ESS TECHNOLOGY INC ,  MALLINSON ANDREW MARTIN ,  DAMPHOUSSE SIMON

Inventor： MALLINSON ANDREW MARTIN ,  DAMPHOUSSE SIMON

IPC: H02H3/05 ,  H03K20060101 ,  H03M3/00 ,  H03K

CPC classification number: H03M3/344 ,  H03M3/358

Abstract: A system and method are provided for compensating for output error in a sigma delta circuit. The system includes an input for receiving an input signal and an output configured to output an output signal. The system further includes a summation component configured to add a first error voltage value, which is derived from an output signal, to an incoming input signal, and a subtraction component configured to subtract a second error voltage value, where the second error voltage value is derived from the adding of a first error voltage value to an incoming input signal.

Abstract translation: 提供了一种用于补偿Σ-Δ电路中的输出误差的系统和方法。 该系统包括用于接收输入信号的输入和被配置为输出输出信号的输出。 该系统还包括一个相加分量，其被配置为将从输出信号导出的第一误差电压值加到输入输入信号;以及减法分量，被配置为减去第二误差电压值，其中第二误差电压值为 从输入输入信号中增加第一误差电压值得出。

公开(公告)号：WO2004004327A1

公开(公告)日：2004-01-08

申请号：PCT/US2003/018569

申请日：2003-06-11

Applicant: ESS TECHNOLOGY, INC. ,  CHAN, Ming, Hong ,  WANG, Haisong

Inventor： CHAN, Ming, Hong ,  WANG, Haisong

IPC: H04N5/781

CPC classification number: G11B31/00 ,  G11B27/105 ,  G11B2220/213 ,  G11B2220/216 ,  G11B2220/218 ,  G11B2220/2545 ,  G11B2220/2562 ,  G11B2220/2575 ,  G11B2220/61 ,  H04N5/783 ,  H04N5/85 ,  H04N9/8042 ,  H04N9/8063

Abstract: The present invention relates to devices and methods for processing data defining a still image slide show with background audio. An example system may include an optical disk player (10) (e.g., DVD player) configured to read video and audio data from one or more storage media (e.g., DVD, compact flash device and/or hard disk (450)). An example method may include presenting output signals containig data descriptive of a slide show with background audio in a mode or configuration selected by a user.

Abstract translation: 本发明涉及用于处理定义具有背景音频的静止图像幻灯片放映的数据的装置和方法。 示例系统可以包括被配置为从一个或多个存储介质（例如，DVD，紧凑型闪存设备和/或硬盘（450））读取视频和音频数据的光盘播放器（10）（例如，DVD播放器）。 示例性方法可以包括以用户选择的模式或配置呈现描述具有背景音频的幻灯片放映的输出信号包含数据。

公开(公告)号：WO2002060261A2

公开(公告)日：2002-08-08

申请号：PCT/US2002/002172

申请日：2002-01-26

Applicant: ESS TECHNOLOGY, INC.

Inventor： MALLINSON, Martin

IPC: A01P

CPC classification number: H03H15/00 ,  G06G7/1928

Abstract: An electronic filter operates as a correlator that provides a discrete approximation of an analog signal. The analog to digital conversion is integrated directly approximation calculation. An array of sample and hold circuits or single bit comparators provide outputs to a series of multipliers, the other input of which is a coefficient value of a Fourier series approximation of the desired frequency response. Each of the sample and hold circuits samples sequentially in time and holds its sample until the next cycle. Thus the sample point rotates in time through the array and each new sample is multiplied by a different coefficient. The output of the multipliers is summed for evaluation.

Abstract translation: 电子滤波器作为提供模拟信号的离散近似的相关器操作。 模数转换是直接逼近计算。 采样和保持电路或单比特比较器的阵列向一系列乘法器提供输出，其另一个输入是所需频率响应的傅立叶级数近似的系数值。 每个采样和保持电路在时间上依次进行采样，并保持其采样直到下一个周期。 因此，采样点在时间上通过阵列旋转，并且每个新采样乘以不同的系数。 乘法器的输出相加以进行求值。

公开(公告)号：WO9953613A9

公开(公告)日：2000-03-16

申请号：PCT/US9908171

申请日：1999-04-14

Applicant: ESS TECHNOLOGY INC

Inventor： SCULLEY TERRY L

IPC: H03G1/00 ,  H03G3/10

CPC classification number: H03G1/0088

Abstract: Two banks of "differently-connected" resistors (R1-R6) that are connected to an input of an op-amp feedback circuit.

Abstract translation: 连接到运算放大器反馈电路的输入的两组“不同连接”电阻（R1-R6）。