公开(公告)号：WO2022072118A1

公开(公告)日：2022-04-07

申请号：PCT/US2021/048994

申请日：2021-09-03

Applicant: QUALCOMM INCORPORATED

Inventor： LIU, Edward Wai Yeung ,  APARIN, Vladimir

IPC: H03M1/00 ,  H03M1/06 ,  H03M1/80 ,  H03M1/08

Abstract: Certain aspects of the present disclosure are directed to a radio frequency digital-to-analog converter (RFDAC). The RFDAC generally includes a plurality of digital-to-analog (DAC) unit cells. At least one DAC unit cell is capable of being configured in an active state or in a sleep state. For the at least one DAC unit cell, an output impedance of the DAC unit cell in the active state is equal to an output impedance of the DAC unit cell in the sleep state.

公开(公告)号：WO2022035715A1

公开(公告)日：2022-02-17

申请号：PCT/US2021/045127

申请日：2021-08-07

Applicant: ANALOG DEVICES, INC.

Inventor： BANDYOPADHYAY, Abhishek ,  BIRDSONG, Preston ,  SPIRER, Adam R.

IPC: H03M1/06 ,  H03M1/66 ,  H03M1/68 ,  H03M1/70 ,  H03M1/74 ,  H03M1/76

Abstract: Systems and methods for a power-efficient 3-level digital-to-analog converter. A converter cell using a current starving technique keeps a portion of the converter cell turned on in a low power mode, as opposed to completely turning off current in selected modes. A conversion system keeps a first set of converters active while allowing a second set of converters to be powered down. Systems and methods presented save power and allow for efficient reactivation of converters.

公开(公告)号：WO2021204387A1

公开(公告)日：2021-10-14

申请号：PCT/EP2020/060142

申请日：2020-04-09

Applicant: ADVANTEST CORPORATION ,  BEERMANN, Andreas ,  MÜCKE, Martin ,  VOLMER, Christian

Inventor： BEERMANN, Andreas ,  MÜCKE, Martin ,  VOLMER, Christian

IPC: H03M1/06 ,  H03M1/66 ,  H04L7/00

Abstract: The invention concerns circuit for converting a signal between digital and analog. According to an aspect of the invention, the circuit comprising: a processor configured to provide or use a synchronizing clock signal; a converter configured to convert a data between digital and analog using a converter clock signal; a phase comparator wherein the phase comparator is configured to determine a phase relationship between the synchronizing clock signal and the converter clock signal; and a digital signal processor coupled to the phase comparator to receive an information about the phase relationship, wherein the digital signal processor is configured to apply a delay to a signal data exchanged between the processor and the converter, in dependence of the phase relationship, wherein there is a predetermined frequency relationship between the synchronizing clock signal and the converter clock signal.

公开(公告)号：WO2021104960A1

公开(公告)日：2021-06-03

申请号：PCT/EP2020/082503

申请日：2020-11-18

Applicant: AMS INTERNATIONAL AG

Inventor： MICHEL, Fridolin

IPC: H03F3/00 ,  H03M1/06 ,  H03M1/16 ,  H03M1/46 ,  G04F10/00 ,  H03M1/56

Abstract: A switched-capacitor amplifier comprises a comparator (110), sample and amplification capacitors (120, 130) and a controller (140) to control charge and discharge current sources (135, 136) in dependence on an output signal of the comparator. A closed loop control circuit (151, 152, 153) is configured to determine the delay of the comparator (110) and control an offset of the comparator in response to the determined delay.

公开(公告)号：WO2021084289A1

公开(公告)日：2021-05-06

申请号：PCT/IB2019/001113

申请日：2019-10-30

Applicant: MICRON TECHNOLOGY, INC.

Inventor： GAROFALO, Pierguido

IPC: H03M1/06 ,  H03M1/08 ,  H03M1/66

Abstract: A method has been disclosed that relates to electrical variability compensation technique for configurable-output circuits. The compensation technique can be applied to a generality of circuits whose output has to vary between two electrical limits spanning the range in between them according to a specific code given as input. A switching sequence that is process gradient-direction agnostic has been disclosed which limits variability. An electric device comprising a processing gradient-direction agnostic configurable-output circuit has been also disclosed.

公开(公告)号：WO2021032767A1

公开(公告)日：2021-02-25

申请号：PCT/EP2020/073161

申请日：2020-08-19

Applicant: TELEDYNE E2V SEMICONDUCTORS SAS

Inventor： BUREAU-SUDREAU, Quentin ,  LIGOZAT, Jérôme ,  LAUBE, Rémi ,  STACKLER, Marc

IPC: H03M1/06 ,  H03M1/66

Abstract: Procédé de synchronisation de données analogiques (Data_ana1, Data_ana2) en sortie d'une pluralité de convertisseurs numérique/analogique (DAC), comprenant au moins un cœur de conversion (C1, C2), sur un front actif d'une horloge de référence commune (Clk) comprenant les étapes suivantes : a) Fournir un signal de synchronisation externe (SYNC_ext), à au moins un convertisseur, et fournir un signal de l'horloge de référence commune à la pluralité de convertisseurs; b) Générer au sein de chaque convertisseur un signal de synchronisation interne (SYNC_int), tel que tous les signaux de synchronisation interne sont alignés sur un front actif de l'horloge de référence commune; c) Pour chacun des convertisseurs, générer un signal de démarrage (START1, START2) représentatif du début de l'envoi de données numériques et compter un nombre de coups d'horloge jusqu'à la génération du signal de synchronisation interne et; d) Appliquer un retard Ri (R1, R2), à chaque cœur de convertisseur, égal à la différence entre le nombre compté le plus élevé dans l'étape c) et le nombre compté pour le cœur. Dispositif pour la mise en œuvre d'un tel procédé.

公开(公告)号：WO2021016323A1

公开(公告)日：2021-01-28

申请号：PCT/US2020/043024

申请日：2020-07-22

Applicant: CIRRUS LOGIC INTERNATIONAL SEMICONDUCTOR LTD. ,  MCFARLAND, James P.

Inventor： MCFARLAND, James P. ,  HEMKUMAR, Nariankadu D. ,  DEO, Sachin ,  DJADI, Younes

IPC: G05B19/042 ,  H03M1/06

Abstract: A system may include a processing engine and an analog-to-digital conversion interface subsystem communicatively coupled to the processing engine. The processing engine may be configured to process feedback data converted from analog feedback data to digital feedback data, wherein the feedback data includes a plurality of data stream sequences converted from the analog feedback data to the digital feedback data at a sample rate and based on processing of the feedback data, generate digital control signals for controlling a system under control. The analog-to-digital conversion interface subsystem may be configured to flexibly control the processing of the processing engine and the generation of digital control signals by the processing engine to minimize latency in the generation of the digital control signals due to processing of the processing engine.

公开(公告)号：WO2020187482A1

公开(公告)日：2020-09-24

申请号：PCT/EP2020/052836

申请日：2020-02-05

Applicant: AMS SENSORS BELGIUM BVBA

Inventor： COTTELEER, Wesley

IPC: H03M1/56 ,  H03M1/12 ,  H03M1/06 ,  H04N5/378 ,  H04N5/376

Abstract: An analog-to-digital converter for an image sensor comprises a counter circuit (110) to generate a respective counter bit (CNT , CNT ,..., CNT ) in response to a counter state of the counter circuit (110), and a storage circuit (130) for storing a respective storage state in response the respective counter bit (CNT , CNT ,..., CNT ). The converter further comprises a comparator circuit (150) for generating a level of a comparison signal (COMP), and a synchronization circuit (160) to generate a write control signal (WRITE) for controlling the storing of the respective storage state in the respective storage cell (140a, 140b,..., 140n). The counter circuit (110) is configured to change the counter state, when a first edge (E1) of a cycle (CY) of the clock signal (CLK) is applied to the counter circuit (110), and to generate the write control signal (WRITE), when a second edge (E2) of the cycle (CY) of the clock signal (CLK) being subsequent to the first edge (E1) of the cycle (CY) of the clock signal (CLK) is applied to the synchronization circuit (160).

公开(公告)号：WO2020105003A1

公开(公告)日：2020-05-28

申请号：PCT/IB2019/060062

申请日：2019-11-22

Applicant: INDIAN INSTITUTE OF SCIENCE

Inventor： THAKUR, Chetan Singh ,  SEELAMANTULA, Chandra Sekhar ,  RUDRESH, Sunil ,  KRISHNA, Adithya ,  SHAW, Vishal

IPC: H03M1/06 ,  H03M1/12 ,  H03M1/18

Abstract: The present disclosure provides a system and method for providing unlimited dynamic range analogue-to-digital conversion. The system includes: a sample-and-hold circuit to sample input analogue signal to generate first set of samples; a modulo circuit configured to compute modulo operation on first set of samples against a reference level to generate set of modulo samples centered about zero; a comparator operatively coupled to the modulo circuit and configured to determine the deviation of the first set of samples based on a comparison of the first set of samples with the reference signal, wherein, when the deviation exceeds a predefined dynamic range, the first set of samples are reset and wrapped to generate reset information pertaining to the deviation; and a quantization unit configured to quantize the generated set of modulo samples to generate a set of output digital samples.

公开(公告)号：WO2020001923A1

公开(公告)日：2020-01-02

申请号：PCT/EP2019/064324

申请日：2019-06-03

Applicant: AMS SENSORS UK LIMITED

Inventor： MICHEL, Fridolin

IPC: G01K7/01 ,  G06K19/07 ,  H03M1/14 ,  H03M1/06 ,  H03M1/08 ,  H03M1/46

Abstract: The temperature sensor comprises first and second diodes (bip 1 , bip 2 ) of specified ratio, the first diode (bip 1 ) being connected between a negative supply voltage and a first resistor (R 1 ) provided for a PTAT voltage (V ptat ) drop, an array of dynamically matched current sources employing a dynamic element matching controller (DEM), the first resistor being connected between the first diode and a first input of the array, the second diode (bip 2 ) being connected between the negative supply voltage and a second input of the array, and a SAR feedback loop, which comprises a SAR controller, a SAR comparator, a generator for a CTAT voltage (V ctat ), and an adjustable second resistor (R 2 ), which implements a DAC and converts the CTAT voltage into a proportional current. The generator for the CTAT voltage is connected to the array of current sources to define a nominal current.