公开(公告)号：WO2004075044A3

公开(公告)日：2006-09-21

申请号：PCT/US2004003027

申请日：2004-02-03

Applicant: SUN MICROSYSTEMS INC ,  TREMBLAY MARC ,  JACOBSON QUINN A ,  CHAUDHRY SHAILDENDER

Inventor： TREMBLAY MARC ,  JACOBSON QUINN A ,  CHAUDHRY SHAILDENDER

IPC: G06F9/38 ,  G06F9/312 ,  G06F9/46 ,  G06F12/08

CPC classification number: G06F12/0862 ,  G06F9/3004 ,  G06F9/30087 ,  G06F9/3834 ,  G06F9/3836 ,  G06F9/3857 ,  G06F9/467 ,  G06F12/0815

Abstract: One embodiment of the present invention provides a system that selectively monitors store instructions to support transactional execution of a process, wherein changes made during the transactional execution are not committed to the architectural state of a processor until the transactional execution successfully completes. Upon encountering a store instruction during transactional execution of a block of instructions, the system determines whether the store instruction is a monitored store instruction or an unmonitored store instruction. If the store instruction is a monitored store instruction, the system performs the store operation, and store-marks a cache line associated with the store instruction to facilitate subsequent detection of an interfering data access to the cache line from another process. If the store instruction is an unmonitored store instruction, the system performs the store operation without store-marking the cache line.

Abstract translation: 本发明的一个实施例提供了一种系统，其选择性地监视存储指令以支持进程的事务性执行，其中在事务执行期间进行的改变不被提交到处理器的体系结构状态，直到事务执行成功完成。 在交易执行指令块期间遇到存储指令时，系统确定存储指令是监视存储指令还是非监视存储指令。 如果存储指令是监视的存储指令，则系统执行存储操作，并存储与存储指令相关联的高速缓存行，以便随后检测到来自另一进程的高速缓存行的干扰数据访问。 如果存储指令是不受监视的存储指令，则系统执行存储操作而不存储标记高速缓存行。

公开(公告)号：WO2005098615A2

公开(公告)日：2005-10-20

申请号：PCT/US2005/010729

申请日：2005-03-30

Applicant: SUN MICROSYSTEMS, INC. ,  TREMBLAY, Marc ,  CHAUDHRY, Shaildender ,  JACOBSON, Quinn A.

Inventor： TREMBLAY, Marc ,  CHAUDHRY, Shaildender ,  JACOBSON, Quinn A.

IPC: G06F9/38

CPC classification number: G06F9/3844 ,  G06F9/30105 ,  G06F9/3838 ,  G06F9/3842 ,  G06F9/3863

Abstract: One embodiment of the present invention provides a system that facilitates storing results of resolvable branches during speculative execution, and then using the results to predict the same branches during non-speculative execution. During operation, the system executes code within a processor. Upon encountering a stall condition, the system speculatively executes the code from the point of the stall, without committing results of the speculative execution to the architectural state of the processor. Upon encountering a branch instruction that is resolved during speculative execution, the system stores the result of the resolved branch in a branch queue, so that the result can be subsequently used to predict the branch during non-speculative execution.

Abstract translation: 本发明的一个实施例提供了一种有助于在推测性执行期间存储可分解分支的结果的系统，然后在非推测性执行期间使用结果来预测相同的分支。 在操作期间，系统在处理器内执行代码。 在遇到停顿状态时，系统从失速点推测地执行代码，而不会将推测性执行的结果提交给处理器的体系结构状态。 在遇到在推测执行期间解析的分支指令时，系统将解析的分支的结果存储在分支队列中，以便随后可以在非推测性执行期间将结果用于预测分支。

公开(公告)号：WO2004075054A1

公开(公告)日：2004-09-02

申请号：PCT/US2004/003667

申请日：2004-02-06

Applicant: SUN MICROSYSTEMS INC. ,  TREMBLAY, Marc ,  JACOBSON, Quinn A. ,  CHAUDHRY, Shaildender

Inventor： TREMBLAY, Marc ,  JACOBSON, Quinn A. ,  CHAUDHRY, Shaildender

IPC: G06F9/46

CPC classification number: G06F9/3863 ,  G06F9/3004 ,  G06F9/30087 ,  G06F9/3834 ,  G06F9/3836 ,  G06F9/3842 ,  G06F9/3857

Abstract: One embodiment of the present invention provides a system that supports executing a fail instruction, which terminates transactional execution of a block of instructions. During operation, the system facilitates transactional execution of a block of instructions within a program, wherein changes made during the transactional execution are not committed to the architectural state of the processor until the transactional execution successfully completes. If a fail instruction is encountered during this transactional execution, the system terminates the transactional execution without committing results of the transactional execution to the architectural state of the processor.

Abstract translation: 本发明的一个实施例提供一种支持执行失败指令的系统，其终止指令块的事务执行。 在操作期间，系统促进程序内的指令块的事务执行，其中在事务执行期间所做的更改不会被提交到处理器的体系结构状态，直到事务执行成功完成。 如果在此事务执行期间遇到失败指令，则系统终止事务执行，而不将事务执行的结果提交给处理器的体系结构状态。

公开(公告)号：WO2004075055A1

公开(公告)日：2004-09-02

申请号：PCT/US2004/003669

申请日：2004-02-06

Applicant: SUN MICROSYSTEMS INC. ,  TREMBLAY, Marc ,  JACOBSON, Quinn, A. ,  CHAUDHRY, Shaildender

Inventor： TREMBLAY, Marc ,  JACOBSON, Quinn, A. ,  CHAUDHRY, Shaildender

IPC: G06F9/46

CPC classification number: G06F9/528 ,  G06F9/3004 ,  G06F9/30087 ,  G06F9/30116 ,  G06F9/3834 ,  G06F9/3836 ,  G06F9/3842 ,  G06F9/3857 ,  Y10S707/99953

Abstract: One embodiment of the present invention supports execution of a start transactional execution (STE) instruction, which marks the beginning of a block of instructions to be executed transactionally. Upon encountering the STE instruction during execution of a program, the system commences transactional execution of the block of instructions following the STE instruction. Changes made during this transactional execution are not committed to the architectural state of the processor until the transactional execution successfully completes.

Abstract translation: 本发明的一个实施例支持开始事务执行（STE）指令的执行，其指示要在事务上执行的指令块的开始。 在执行程序期间遇到STE指令时，系统开始按照STE指令执行指令块的事务性执行。 在事务执行之前进行的更改不会在事务执行成功完成之前提交到处理器的体系结构状态。

公开(公告)号：WO2004075046A3

公开(公告)日：2004-09-02

申请号：PCT/US2004/003668

申请日：2004-02-06

Applicant: SUN MICROSYSTEMS INC. ,  TREMBLAY, Marc ,  JACOBSON, Quinn A. ,  CHAUDHRY, Shaildender ,  MOIR, Mark S. ,  HERLIHY, Maurice P.

Inventor： TREMBLAY, Marc ,  JACOBSON, Quinn A. ,  CHAUDHRY, Shaildender ,  MOIR, Mark S. ,  HERLIHY, Maurice P.

IPC: G06F9/38

Abstract: One embodiment of the present invention provides a system that facilitates selectively unmarking load-marked cache lines during transactional program execution, wherein load-marked cache lines are monitored during transactional execution to detect interfering accesses from other threads. During operation, the system encounters a release instruction during transactional execution of a block of instructions. In response to the release instruction, the system modifies the state of cache lines, which are specially load-marked to indicate they can be released from monitoring, to account for the release instruction being encountered. In doing so, the system can potentially cause the specially load-marked cache lines to become unmarked. In a variation on this embodiment, upon encountering a commit-and­startnew-transaction instruction, the system modifies load-marked cache lines to account for the commit-and-start­new-transaction instruction being encountered. In doing so, the system causes normally load-marked cache lines to become unmarked, while other specially load-marked cache lines may remain load-marked past the commit-and­startnew-transaction instruction.

公开(公告)号：WO2004075046A2

公开(公告)日：2004-09-02

申请号：PCT/US2004003668

申请日：2004-02-06

Applicant: SUN MICROSYSTEMS INC ,  TREMBLAY MARC ,  JACOBSON QUINN A ,  CHAUDHRY SHAILDENDER ,  MOIR MARK S ,  HERLIHY MAURICE P

Inventor： TREMBLAY MARC ,  JACOBSON QUINN A ,  CHAUDHRY SHAILDENDER ,  MOIR MARK S ,  HERLIHY MAURICE P

IPC: G06F9/30 ,  G06F9/312 ,  G06F9/38 ,  G06F9/46 ,  G06F12/08

CPC classification number: G06F12/0815 ,  G06F9/3004 ,  G06F9/30087 ,  G06F9/3834 ,  G06F9/3836 ,  G06F9/3842 ,  G06F9/3851 ,  G06F9/3857 ,  G06F9/3863 ,  G06F9/467 ,  G06F12/0862

Abstract: One embodiment of the present invention provides a system that facilitates selectively unmarking load-marked cache lines during transactional program execution, wherein load-marked cache lines are monitored during transactional execution to detect interfering accesses from other threads. During operation, the system encounters a release instruction during transactional execution of a block of instructions. In response to the release instruction, the system modifies the state of cache lines, which are specially load-marked to indicate they can be released from monitoring, to account for the release instruction being encountered. In doing so, the system can potentially cause the specially load-marked cache lines to become unmarked. In a variation on this embodiment, upon encountering a commit-and­startnew-transaction instruction, the system modifies load-marked cache lines to account for the commit-and-start­new-transaction instruction being encountered. In doing so, the system causes normally load-marked cache lines to become unmarked, while other specially load-marked cache lines may remain load-marked past the commit-and­startnew-transaction instruction.

Abstract translation: 本发明的一个实施例提供了一种系统，其有助于在事务性程序执行期间有选择地取消标记加载标记的高速缓存行，其中负责标记的高速缓存行在事务执行期间被监视以检测来自其他线程的干扰访问。 在操作期间，系统在事务处理指令块期间遇到释放指令。 响应于释放指令，系统修改高速缓存行的状态，这些高速缓存行被特别加载标记以指示它们可以从监视释放，以解决遇到的释放指令。 在这样做时，系统可能会导致特别加载标记的高速缓存行变为未标记。 在本实施例的变型中，在遇到提交和新建事务指令时，系统修改加载标记的高速缓存行以解决遇到的提交和启动新事务指令。 在这样做时，系统会导致正常加载标记的高速缓存行变为未标记，而其他特别加载标记的高速缓存行可能会通过commit-andstartnew-transaction指令保持加载标记。