Abstract:
A method, system, and computer program product are provided for prioritizing transactions. A processor in a computing environment initiates the execution of a transaction. The processor includes a transactional core, and the execution of the transaction is performed by the transactional core. The processor obtains concurrent with the execution of the transaction by the transactional core, an indication of a conflict between the transaction and at least one other transaction being executed by an additional core in the computing environment. The processor determines if the transactional core includes an indicator and based on determining that the transactional core includes an indicator, the processor ignores the conflict and utilizing the transactional core to complete executing the transaction.
Abstract:
A group of memory modules in a memory system receives a memory operation instruction comprising instructions on a memory operation and sends votes on the possibility to perform the memory operation to a memory coordinator module. The memory coordinator module receives votes and establishes a list of memory modules which have voted positively. The memory coordinator module verifies that the list of memory modules comprises all the memory modules in the group and that there is not another memory coordinator module detected by the memory coordinator module, instructs all the memory modules in the group to commit to the memory operation.
Abstract:
Adaptive queued locking for control of speculative execution is disclosed. An example apparatus includes a lock to: enforce a first quota to control a number of threads allowed to concurrently speculatively execute after being placed in a queue; and in response to the first quota not having been reached, enable a first thread from the queue to speculatively execute; and an adjuster to change a first value of the first quota based on a result of the speculative execution of the first thread.
Abstract:
Technologies for detecting unauthorized memory accesses include a computing device with a processor having transactional memory support. The computing device executes a security assistance thread that starts a transaction using the transactional memory support. Within the transaction, the security assistance thread writes arbitrary data to one or more monitored memory locations. The security assistance thread waits without committing the transaction. The security assistance thread may loop endlessly. The transactional memory support of the computing device detects a transactional abort caused by an external read of the monitored memory location. The computing device analyzes the transactional abort and determines whether a security event has occurred. The computing device performs a security response if a security event has occurred. The monitored memory locations may include memory-mapped operating system libraries, kernel data structures, executable images, or other memory structures that may be scanned by malicious software. Other embodiments are described and claimed.
Abstract:
An apparatus and method are described for a hardware transactional memory (HTM) profiler. For example, one embodiment of an apparatus comprises a transactional debugger (TDB) recording module to record data related to the execution of transactional memory program code, including data related to the execution of branches and transactional events in the transactional memory program code; and a profiler to analyze portions of the recorded data using trace-based replay techniques to responsively generate profile data comprising transaction-level events and function-level conflict data usable to optimize the transactional memory program code.
Abstract:
A data processing apparatus (4) includes processing circuitry (6) for executing program instructions that form part of a transaction which executes to generate speculative updates and to commit the speculative updates if the transaction completes without a conflict. Instruction sampling circuitry (44) captures instruction diagnostic data (IDD) relating to execution of a sampled instruction. Transaction tracking circuitry (46) detects if the sampled instruction is within a transaction and if so, tracks whether the speculative updates associated with the transaction are committed and captures transaction diagnostic data (TDD) indicative of whether or not the speculative updates were committed. Thus, both instruction diagnostic data relating to a sampled instruction and transaction diagnostic data relating to the fate of a transaction containing a sampled instruction are captured.
Abstract:
A data processing system supporting execution of transactions comprising one or more program instructions that execute to generate speculative updates is provided. The speculative updates are committed in normal operation if the transaction completes without a conflict. Start of execution of a transaction may be detected and execution diverted to be performed by software emulation rather than direct execution by the processing hardware. The software emulation may store data representing one or more versions of the speculative updates generated during the emulation. The software emulation may also detect conflicts with the transaction being emulated. In order to facilitate modifying the behaviour of other parts of the system interacting with a transaction under investigation, a non-standard response signal may be returned in response to a detected memory access request to a transaction being emulated. The non-standard response signal may be used to initiate the request source to follow a subsequent path of processing different from that which it would otherwise follow. Support is also provided for detecting a trigger condition which results in the halting (freezing) of a partially completed transaction and the saving the speculative updates associated with that partially completed transaction to the architectural state of the system.
Abstract:
A system and method can support across-domain messaging in a transactional middleware machine environment. A transaction domain can import one or more services from a remote transaction domain, wherein said one or more services are registered in a service table that is associated with the transaction domain. Furthermore, a client in the transaction domain can find from the service table a remote server in the remote transaction domain that provides said one or more services, and send a message directly to the remote server to invoke said one or more services by passing one or more domain gateway servers in both the transaction domain and the remote transaction domain.
Abstract:
Système de calcul distribué comprenant une pluralité d'unités de calcul (UC) et une mémoire partagée (MP) entre lesdites unités de calcul, caractérisé en ce qu'il comprend au moins un module matériel de détection des conflits d'accès (INSP) desdites unités de calcul à ladite mémoire partagée; ledit ou chaque dit module matériel de détection des conflits étant configuré pour : mémoriser au moins une structure de données probabiliste, indicative de la totalité des adresses de ladite mémoire partagée impliquées dans la totalité des transactions en cours; recevoir au moins un message indicatif d'une requête d'accès, par une dite unité de calcul, à au moins une adresse de ladite mémoire partagée; déterminer, à partir de ladite structure de données probabiliste, si ladite adresse est déjà impliquée dans une transaction en cours, et transmettre à ladite unité de calcul un message de présence ou absence de conflits d'accès; recevoir au moins un message indicatif ou confirmatif d'une réservation ou d'une libération d'au moins une dite adresse de ladite mémoire partagée, et mettre à jour ladite structure de données probabiliste pour que les adresses réservées et les adresses libérées soient considérées, respectivement, comme étant/n'étant pas impliquées dans une transaction en cours. Procédé d'utilisation d'un tel système.
Abstract:
Generally, this disclosure provides systems, devices, methods and computer readable media for software polling elision with restricted transactional memory. The device may include a restricted transactional memory (RTM) processor configured to monitor a region associated with a transaction and to enable an abort of the transaction, wherein the abort nullifies modifications to the region, the modifications associated with processing within the transaction prior to the abort. The device may also include a code module configured to: produce a first request; send the first request to an external processing entity; enter the transaction; produce a second request; commit the transaction in response to a completion indication from the external processing entity; and abort the transaction in response to a non-completion indication from the external entity. Software polling elision avoids the latency, and efficiency can be increased.