公开(公告)号：WO2005098613A3

公开(公告)日：2006-07-13

申请号：PCT/US2005010730

申请日：2005-03-30

Applicant: SUN MICROSYSTEMS INC ,  TREMBLAY MARC ,  CHAUDHRY SHAILDENDER ,  JACOBSON QUINN A

Inventor： TREMBLAY MARC ,  CHAUDHRY SHAILDENDER ,  JACOBSON QUINN A

IPC: G06F9/38 ,  G06F9/00

CPC classification number: G06F9/383 ,  G06F9/3838 ,  G06F9/3842 ,  G06F9/3863

Abstract: A processor that facilitates rapid progress while speculatively executing instructions in scout mode. During normal operation, the processor executes instructions in a normal execution mode. Upon encountering a stall condition, the processor executes the instructions in a scout mode, wherein the instructions are speculatively executed to prefetch future loads, but wherein results are not committed to the architectural state of the processor. While speculatively executing the instructions in scout mode, the processor maintains dependency information for each register indicating whether or not a value in the register depends on an unresolved data-dependency. If an instruction to be executed in scout mode depends on an unresolved data dependency, the processor executes the instruction as a NOOP so that the instruction executes rapidly without tying up computational resources. The processor also propagates dependency information indicating an unresolved data dependency to a destination register for the instruction.

Abstract translation: 在侦察模式下推测执行指令时，可以促进快速进展的处理器。 在正常操作期间，处理器以正常执行模式执行指令。 在遇到停顿状态时，处理器以侦察模式执行指令，其中推测性地执行指令以预取将来的负载，但是其中结果未被提交到处理器的架构状态。 当在侦察模式中推测性地执行指令时，处理器维护每个寄存器的依赖性信息，指示寄存器中的值是否取决于未解决的数据依赖性。 如果以侦察模式执行的指令取决于未解决的数据依赖性，则处理器将该指令作为NOOP执行，以使指令快速执行，而不占用计算资源。 处理器还将指示未解决的数据依赖关系的依赖信息传播到指令的目的地寄存器。

公开(公告)号：WO2004075045A2

公开(公告)日：2004-09-02

申请号：PCT/US2004/003028

申请日：2004-02-03

Applicant: SUN MICROSYSTEMS INC. ,  TREMBLAY, Marc ,  JACOBSON, Quinn, A. ,  CHAUDHRY, Shaildender

Inventor： TREMBLAY, Marc ,  JACOBSON, Quinn, A. ,  CHAUDHRY, Shaildender

IPC: G06F9/38

CPC classification number: G06F12/0862 ,  G06F9/3004 ,  G06F9/30087 ,  G06F9/3834 ,  G06F9/3836 ,  G06F9/3857 ,  G06F9/467 ,  G06F12/0815 ,  G06F12/0842

Abstract: One embodiment of the present invention provides a system that selectively monitors load instructions to support transactional execution of a process, wherein changes made during the transactional execution are not committed to the architectural state of a processor until the transactional execution successfully completes. Upon encountering a load instruction during transactional execution of a block of instructions, the system determines whether the load instruction is a monitored load instruction or an unmonitored load instruction. If the load instruction is a monitored load instruction, the system performs the load operation, and load-marks a cache line associated with the load instruction to facilitate subsequent detection of an interfering data access to the cache line from another process. If the load instruction is an unmonitored load instruction, the system performs the load operation without load-marking the cache line.

Abstract translation: 本发明的一个实施例提供了一种系统，其选择性地监视加载指令以支持进程的事务性执行，其中在事务执行期间进行的改变不被提交到处理器的体系结构状态，直到事务执行成功完成。 在执行指令块的事务执行期间遇到加载指令时，系统确定加载指令是监视加载指令还是不受监控的加载指令。 如果加载指令是被监视的加载指令，则系统执行加载操作，并加载标记与加载指令相关联的高速缓存行，以便随后检测到来自另一进程的高速缓存行的干扰数据访问。 如果加载指令是不受监控的加载指令，则系统将执行加载操作，而不加载标记缓存行。

公开(公告)号：WO2004075044A2

公开(公告)日：2004-09-02

申请号：PCT/US2004/003027

申请日：2004-02-03

Applicant: SUN MICROSYSTEMS INC. ,  TREMBLAY, Marc ,  JACOBSON, Quinn, A. ,  CHAUDHRY, Shaildender

Inventor： TREMBLAY, Marc ,  JACOBSON, Quinn, A. ,  CHAUDHRY, Shaildender

IPC: G06F9/38

CPC classification number: G06F12/0862 ,  G06F9/3004 ,  G06F9/30087 ,  G06F9/3834 ,  G06F9/3836 ,  G06F9/3857 ,  G06F9/467 ,  G06F12/0815

Abstract: One embodiment of the present invention provides a system that selectively monitors store instructions to support transactional execution of a process, wherein changes made during the transactional execution are not committed to the architectural state of a processor until the transactional execution successfully completes. Upon encountering a store instruction during transactional execution of a block of instructions, the system determines whether the store instruction is a monitored store instruction or an unmonitored store instruction. If the store instruction is a monitored store instruction, the system performs the store operation, and store-marks a cache line associated with the store instruction to facilitate subsequent detection of an interfering data access to the cache line from another process. If the store instruction is an unmonitored store instruction, the system performs the store operation without store-marking the cache line.

Abstract translation: 本发明的一个实施例提供了一种系统，其选择性地监视存储指令以支持进程的事务性执行，其中在事务执行期间进行的改变不被提交到处理器的体系结构状态，直到事务执行成功完成。 在交易执行指令块期间遇到存储指令时，系统确定存储指令是监视存储指令还是非监视存储指令。 如果存储指令是监视的存储指令，则系统执行存储操作，并存储与存储指令相关联的高速缓存行，以便随后检测到来自另一进程的高速缓存行的干扰数据访问。 如果存储指令是不受监视的存储指令，则系统执行存储操作而不存储标记高速缓存行。

公开(公告)号：WO2007078920A1

公开(公告)日：2007-07-12

申请号：PCT/US2006/048278

申请日：2006-12-18

Applicant: INTEL CORPORATION ,  JACOBSON, Quinn, A. ,  SRINIVAS, Suresh ,  BRACY, Anne, C. ,  WANG, Hong

Inventor： JACOBSON, Quinn, A. ,  SRINIVAS, Suresh ,  BRACY, Anne, C. ,  WANG, Hong

IPC: G06F12/02

CPC classification number: G06F12/0802 ,  G06F12/0269

Abstract: A method and apparatus for hardware-based dynamic escape detection in managed run-time environments are described. In one embodiment, the method includes the detection of a pointer update of a first object having a global scope. In one embodiment, a single instruction is issued to assert that a scope attribute associated with a target object of the pointer update identifies a global scope. The single instruction may return failure if the scope attribute that is associated with the second object identifies the scope of the second object as local. Verification may include the reading of an object descriptor for the second object to determine whether a scope attribute of the object descriptor indicates that the scope of the second object is local. Once verified, in one embodiment, the second object, and each object reachable from the second object, are converted into global objects. Other embodiments are described and claimed.

Abstract translation: 描述了在受管理的运行时环境中用于基于硬件的动态逃逸检测的方法和装置。 在一个实施例中，该方法包括检测具有全局范围的第一对象的指针更新。 在一个实施例中，发出单个指令以断言与指针更新的目标对象相关联的范围属性标识全局范围。 如果与第二个对象相关联的范围属性将第二个对象的范围标识为本地，那么单个指令可能会返回失败。 验证可以包括读取第二对象的对象描述符，以确定对象描述符的范围属性是否指示第二对象的范围是本地的。 一旦验证，在一个实施例中，第二对象和从第二对象可访问的每个对象被转换成全局对象。 描述和要求保护其他实施例。

公开(公告)号：WO2005098613A2

公开(公告)日：2005-10-20

申请号：PCT/US2005/010730

申请日：2005-03-30

Applicant: SUN MICROSYSTEMS, INC. ,  TREMBLAY, Marc ,  CHAUDHRY, Shaildender ,  JACOBSON, Quinn A.

Inventor： TREMBLAY, Marc ,  CHAUDHRY, Shaildender ,  JACOBSON, Quinn A.

IPC: G06F9/00

CPC classification number: G06F9/383 ,  G06F9/3838 ,  G06F9/3842 ,  G06F9/3863

Abstract: A processor that facilitates rapid progress while speculatively executing instructions in scout mode. During normal operation, the processor executes instructions in a normal execution mode. Upon encountering a stall condition, the processor executes the instructions in a scout mode, wherein the instructions are speculatively executed to prefetch future loads, but wherein results are not committed to the architectural state of the processor. While speculatively executing the instructions in scout mode, the processor maintains dependency information for each register indicating whether or not a value in the register depends on an unresolved data-dependency. If an instruction to be executed in scout mode depends on an unresolved data dependency, the processor executes the instruction as a NOOP so that the instruction executes rapidly without tying up computational resources. The processor also propagates dependency information indicating an unresolved data dependency to a destination register for the instruction.

Abstract translation: 在侦察模式下推测执行指令时，可以促进快速进展的处理器。 在正常操作期间，处理器以正常执行模式执行指令。 在遇到停顿状态时，处理器以侦察模式执行指令，其中推测性地执行指令以预取将来的负载，但是其中结果未被提交到处理器的架构状态。 当在侦察模式中推测性地执行指令时，处理器维护每个寄存器的依赖性信息，指示寄存器中的值是否取决于未解决的数据依赖性。 如果以侦察模式执行的指令取决于未解决的数据依赖性，则处理器将该指令作为NOOP执行，以使指令快速执行，而不占用计算资源。 处理器还将指示未解决的数据依赖关系的依赖信息传播到指令的目的地寄存器。

公开(公告)号：WO2004075051A1

公开(公告)日：2004-09-02

申请号：PCT/US2004/002684

申请日：2004-01-30

Applicant: SUN MICROSYSTEMS INC. ,  CHAUDHRY, Shaildender ,  TREMBLAY, Marc ,  JACOBSON, Quinn, A.

Inventor： CHAUDHRY, Shaildender ,  TREMBLAY, Marc ,  JACOBSON, Quinn, A.

IPC: G06F9/46

CPC classification number: G06F12/0862 ,  G06F9/30116 ,  G06F9/3842 ,  G06F9/3857 ,  G06F9/3863 ,  G06F9/528 ,  G06F12/0815 ,  G06F12/0842

Abstract: One embodiment of the present invention provides a system that facilitates avoiding locks by speculatively executing critical sections of code. During operation, the system allows a process to speculatively execute a critical section of code within a program without first acquiring a lock associated with the critical section. If the process subsequently completes the critical section without encountering an interfering data access from another process, the system commits changes made during the speculative execution, and resumes normal non-speculative execution of the program past the critical section. Otherwise, if an interfering data access from another process is encountered during execution of the critical section, the system discards changes made during the speculative execution, and attempts to re-execute the critical section.

Abstract translation: 本发明的一个实施例提供一种通过推测性地执行代码的关键部分来有助于避免锁定的系统。 在操作期间，系统允许进程在程序中推测性地执行代码的关键部分而不首先获得与关键部分相关联的锁定。 如果该过程随后完成关键部分而没有遇到来自另一进程的干扰数据访问，则系统进行在推测执行期间所做的更改，并且通过关键部分恢复程序的正常非推测性执行。 否则，如果在执行关键部分期间遇到来自其他进程的干扰数据访问，则系统将丢弃在推测执行期间所做的更改，并尝试重新执行临界部分。

公开(公告)号：WO2005098615A3

公开(公告)日：2006-06-29

申请号：PCT/US2005010729

申请日：2005-03-30

Applicant: SUN MICROSYSTEMS INC ,  TREMBLAY MARC ,  CHAUDHRY SHAILDENDER ,  JACOBSON QUINN A

Inventor： TREMBLAY MARC ,  CHAUDHRY SHAILDENDER ,  JACOBSON QUINN A

IPC: G06F9/38 ,  G06F9/00

CPC classification number: G06F9/3844 ,  G06F9/30105 ,  G06F9/3838 ,  G06F9/3842 ,  G06F9/3863

Abstract: One embodiment of the present invention provides a system that facilitates storing results of resolvable branches during speculative execution, and then using the results to predict the same branches during non-speculative execution. During operation, the system executes code within a processor. Upon encountering a stall condition, the system speculatively executes the code from the point of the stall, without committing results of the speculative execution to the architectural state of the processor. Upon encountering a branch instruction that is resolved during speculative execution, the system stores the result of the resolved branch in a branch queue, so that the result can be subsequently used to predict the branch during non-speculative execution.

Abstract translation: 本发明的一个实施例提供了一种有助于在推测性执行期间存储可分解分支的结果的系统，然后在非推测性执行期间使用结果来预测相同的分支。 在操作期间，系统在处理器内执行代码。 在遇到停顿状态时，系统从失速点推测地执行代码，而不会将推测性执行的结果提交给处理器的体系结构状态。 在遇到在推测执行期间解析的分支指令时，系统将解析的分支的结果存储在分支队列中，以便随后可以在非推测性执行期间将结果用于预测分支。

公开(公告)号：WO2004075045A3

公开(公告)日：2005-08-11

申请号：PCT/US2004003028

申请日：2004-02-03

Applicant: SUN MICROSYSTEMS INC ,  TREMBLAY MARC ,  JACOBSON QUINN A ,  CHAUDHRY SHAILDENDER

Inventor： TREMBLAY MARC ,  JACOBSON QUINN A ,  CHAUDHRY SHAILDENDER

IPC: G06F9/46 ,  G06F12/08 ,  G06F9/38

CPC classification number: G06F12/0862 ,  G06F9/3004 ,  G06F9/30087 ,  G06F9/3834 ,  G06F9/3836 ,  G06F9/3857 ,  G06F9/467 ,  G06F12/0815 ,  G06F12/0842

Abstract: One embodiment of the present invention provides a system that selectively monitors load instructions to support transactional execution of a process, wherein changes made during the transactional execution are not committed to the architectural state of a processor until the transactional execution successfully completes. Upon encountering a load instruction during transactional execution of a block of instructions, the system determines whether the load instruction is a monitored load instruction or an unmonitored load instruction. If the load instruction is a monitored load instruction, the system performs the load operation, and load-marks a cache line associated with the load instruction to facilitate subsequent detection of an interfering data access to the cache line from another process. If the load instruction is an unmonitored load instruction, the system performs the load operation without load-marking the cache line.

Abstract translation: 本发明的一个实施例提供了一种系统，其选择性地监视加载指令以支持进程的事务性执行，其中在事务执行期间进行的改变不被提交到处理器的体系结构状态，直到事务执行成功完成。 在执行指令块的事务执行期间遇到加载指令时，系统确定加载指令是监视加载指令还是不受监控的加载指令。 如果加载指令是被监视的加载指令，则系统执行加载操作，并加载标记与加载指令相关联的高速缓存行，以便随后检测到来自另一进程的高速缓存行的干扰数据访问。 如果加载指令是不受监控的加载指令，则系统将执行加载操作，而不加载标记缓存行。

公开(公告)号：WO2004075053A1

公开(公告)日：2004-09-02

申请号：PCT/US2004/003182

申请日：2004-02-04

Applicant: SUN MICROSYSTEMS INC. ,  TREMBLAY, Marc ,  JACOBSON, Quinn, A. ,  CHAUDHRY, Shaildender

Inventor： TREMBLAY, Marc ,  JACOBSON, Quinn, A. ,  CHAUDHRY, Shaildender

IPC: G06F9/46

CPC classification number: G06F9/3834 ,  G06F9/3004 ,  G06F9/30087 ,  G06F9/3836 ,  G06F9/3842 ,  G06F9/3851 ,  G06F9/3857 ,  G06F9/467 ,  G06F12/0815 ,  G06F12/0862

Abstract: One embodiment of the present invention provides a system that facilitates executing a commit instruction, which marks the end of a block of instructions to be executed transactionally. Upon encountering the commit instruction during execution of a program, the system successfully completes transactional execution of the block of instructions preceding the commit instruction. Changes made during the transactional execution are not committed to the architectural state of the processor until the transactional execution successfully completes.

Abstract translation: 本发明的一个实施例提供了一种便于执行提交指令的系统，该指令标记要在事务上执行的指令块的结束。 在执行程序期间遇到提交指令时，系统成功完成了提交指令之前的指令块的事务执行。 在事务执行之前进行的更改在事务执行成功完成之前不会提交到处理器的体系结构状态。

公开(公告)号：WO2004075052A1

公开(公告)日：2004-09-02

申请号：PCT/US2004/002685

申请日：2004-01-30

Applicant: SUN MICROSYSTEMS INC. ,  CHAUDHRY, Shaildender ,  TREMBLAY, Marc ,  JACOBSON, Quinn, A.

Inventor： CHAUDHRY, Shaildender ,  TREMBLAY, Marc ,  JACOBSON, Quinn, A.

IPC: G06F9/46

CPC classification number: G06F12/0862 ,  G06F9/3004 ,  G06F9/30087 ,  G06F9/30105 ,  G06F9/30116 ,  G06F9/3834 ,  G06F9/3836 ,  G06F9/3842 ,  G06F9/3851 ,  G06F9/3857 ,  G06F9/3861 ,  G06F9/467 ,  G06F12/0815 ,  G06F12/0842

Abstract: One embodiment of the present invention provides a system that facilitates delaying interfering memory accesses from other threads during transactional execution. During transactional execution of a block of instructions, the system receives a request from another thread (or processor) to perform a memory access involving a cache line. If performing the memory access on the cache line will interfere with the transactional execution and if it is possible to delay the memory access, the system delays the memory access and stores copy-back information for the cache line to enable the cache line to be copied back to the requesting thread. At a later time, when the memory access will no longer interfere with the transactional execution, the system performs the memory access and copies the cache line back to the requesting thread.

Abstract translation: 本发明的一个实施例提供了一种在事务执行期间有助于延迟来自其他线程的干扰存储器访问的系统。 在一个指令块的事务执行期间，系统从另一个线程（或处理器）接收到执行涉及高速缓存线的存储器访问的请求。 如果执行高速缓存行上的存储器访问将干扰事务执行，并且如果可以延迟存储器访问，则系统延迟存储器访问并存储用于高速缓存行的复制信息以使得能够复制高速缓存行 回到请求线程。 在稍后的时间，当内存访问不再干扰事务执行时，系统执行内存访问并将缓存行复制回请求的线程。