公开(公告)号：WO2004044762A2

公开(公告)日：2004-05-27

申请号：PCT/US2003/034833

申请日：2003-10-30

Applicant: NEWISYS, INC.

Inventor： WATSON, Charles, E., Jr ,  KOTA, Rajesh ,  GLASCO, David, B.

IPC: G06F15/16

CPC classification number: G06F13/4022 ,  G06F12/0815 ,  G06F15/17337 ,  G06F15/80 ,  G06F2212/621 ,  H04L69/12 ,  H04L69/18

Abstract: A multi-processor computer system is described in which transaction processing in each cluster of processors is distributed among multiple protocol engines. Each cluster includes a plurality of local nodes and an interconnection controller interconnected by a local point-to-point architecture. The interconnection controller in each cluster comprises a plurality of protocol engines for processing transactions. Transactions are distributed among the protocol engines using destination information associated with the transactions.

Abstract translation: 描述了一种多处理器计算机系统，其中每个处理器集群中的事务处理分布在多个协议引擎中。 每个集群包括多个本地节点和通过本地点对点架构互连的互连控制器。 每个集群中的互连控制器包括用于处理事务的多个协议引擎。 使用与事务相关联的目的地信息在协议引擎之间分配事务。

公开(公告)号：WO2004042585A2

公开(公告)日：2004-05-21

申请号：PCT/US2003/034756

申请日：2003-10-30

Applicant: NEWISYS, INC.

Inventor： GLASCO, David, B.

IPC: G06F12/08

CPC classification number: G06F12/0817

Abstract: According to the present invention, methods and apparatus are provided for increasing the efficiency of data access in a multiple processor, multiple cluster system. Mechanisms for reducing the number of transactions in a multiple cluster system are provided. In one example, probe filter information is used to limit the number of probe requests transmitted to request and remote clusters.

Abstract translation: 根据本发明，提供了用于提高多处理器，多集群系统中的数据访问效率的方法和装置。 提供了减少多个集群系统中的事务数量的机制。 在一个示例中，探测器过滤器信息用于限制发送到请求和远程集群的探测请求的数量。

公开(公告)号：WO2005003893A3

公开(公告)日：2007-02-15

申请号：PCT/US2004019524

申请日：2004-06-18

Applicant: NEWISYS INC ,  KOTA RAJESH ,  NEWAWARKER SHASHANK ,  PRASADH GURU ,  ZEITLER CARL ,  GLASCO DAVID B

Inventor： KOTA RAJESH ,  NEWAWARKER SHASHANK ,  PRASADH GURU ,  ZEITLER CARL ,  GLASCO DAVID B

IPC: G06F15/16 ,  G06F20060101 ,  G06F15/00 ,  G06F15/177 ,  G06F15/76

CPC classification number: G06F15/16

Abstract: According to the present invention, methods and apparatus are provided to allow dynamic multiple cluster system configuration changes. In one example, processors in the multiple cluster system share a virtual address space. Mechanisms for dynamically introducing and removing processors, I/O resources, and clusters are provided. The mechanisms can be implemented during reset or while a system is operating. Links can be dynamically enabled or disabled.

Abstract translation: 根据本发明，提供了用于允许动态多集群系统配置改变的方法和装置。 在一个示例中，多个集群系统中的处理器共享虚拟地址空间。 提供了动态引入和删除处理器，I / O资源和集群的机制。 这些机制可以在复位期间或系统运行时实现。 链接可以动态启用或禁用。

公开(公告)号：WO2004044762A3

公开(公告)日：2006-02-09

申请号：PCT/US0334833

申请日：2003-10-30

Applicant: NEWISYS INC

Inventor： WATSON CHARLES E JR ,  KOTA RAJESH ,  GLASCO DAVID B

IPC: G06F15/173 ,  H04L29/06

CPC classification number: G06F13/4022 ,  G06F12/0815 ,  G06F15/17337 ,  G06F15/80 ,  G06F2212/621 ,  H04L69/12 ,  H04L69/18

Abstract: A multi-processor computer system is described in which transaction processing in each cluster of processors is distributed among multiple protocol engines. Each cluster includes a plurality of local nodes and an interconnection controller interconnected by a local point-to-point architecture. The interconnection controller in each cluster comprises a plurality of protocol engines for processing transactions. Transactions are distributed among the protocol engines using destination information associated with the transactions.

Abstract translation: 描述了一种多处理器计算机系统，其中每个处理器集群中的事务处理分布在多个协议引擎中。 每个集群包括多个本地节点和通过本地点对点架构互连的互连控制器。 每个集群中的互连控制器包括用于处理事务的多个协议引擎。 使用与事务相关联的目的地信息在协议引擎之间分配事务。

公开(公告)号：WO2005077057A3

公开(公告)日：2006-02-02

申请号：PCT/US2005004118

申请日：2005-02-08

Applicant: NEWISYS INC ,  KHALEEL ADNAN

Inventor： KHALEEL ADNAN

IPC: G06F11/30

CPC classification number: G06F11/3419 ,  G06F11/3404 ,  G06F2201/87 ,  G06F2201/88

Abstract: Methods and apparatus are described for measuring latency in computer systems. A computer system includes a processor, memory, and I/O. The processor is operable to initiate transactions involving the memory and the I/O. The computer system further includes a latency counter operable to measure a latency for each of selected ones of the transactions. The system also includes a plurality of histogram counters. Each histogram counter is operable to count the latencies corresponding to an associated latency range.

Abstract translation: 描述了用于测量计算机系统中的延迟的方法和装置。 计算机系统包括处理器，存储器和I / O。 处理器可操作以启动涉及存储器和I / O的事务。 计算机系统还包括可操作用于测量每个所选事务中的每一个的等待时间的等待时间计数器。 该系统还包括多个直方图计数器。 每个直方图计数器可操作以对与相应的等待时间范围相对应的延迟进行计数。

公开(公告)号：WO2004070619A3

公开(公告)日：2005-04-28

申请号：PCT/US0334834

申请日：2003-10-30

Applicant: NEWISYS INC

Inventor： ZEITLER CARL ,  GLASCO DAVID B ,  RECORD LES ,  OEHLER RICHARD R ,  KULPA WILLIAM G ,  PRASADH GURU ,  KOTA RAJESH

IPC: G06F1/18 ,  G06F1/24 ,  G06F1/32

CPC classification number: G06F1/189 ,  G06F1/24

Abstract: Methods and apparatus are provided for improving the distribution of system management signals within a computer system complex. Mechanisms are provided for transmission both within a box and between computer system boxes. Local routing tables and general routing tables allow the distribution of system management signals precisely to resources associated with particular partitions. Signals are sequenced to put resources associated with one or more boxes in the appropriate states. The distribution of signals between boxes in the computer system complex can be accomplished with the use of a dedicated wire.

Abstract translation: 提供了用于改善计算机系统综合体内的系统管理信号的分布的方法和装置。 提供了在盒子内和计算机系统盒之间传输的机构。 本地路由表和一般路由表允许将系统管理信号精确地分配给与特定分区相关联的资源。 对信号进行排序，将与一个或多个框相关联的资源放入适当的状态。 可以使用专用线来实现计算机系统中的盒子之间的信号分配。

公开(公告)号：WO2005017755A1

公开(公告)日：2005-02-24

申请号：PCT/US2004/024685

申请日：2004-07-29

Applicant: NEWISYS, INC. ,  GLASCO, David, B.

Inventor： GLASCO, David, B.

IPC: G06F12/00

CPC classification number: G06F12/0831 ,  G06F12/0813 ,  G06F12/082

Abstract: According to the present invention, methods and apparatus are provided for increasing the efficiency of data access in a multiple processor, multiple cluster system. Mechanisms for allowing a variety of transactions to complete locally are implemented by providing remote data caches associated with the various clusters in the system. The remote data caches receive data and state information for memory lines held in remote clusters. If information for responding to a request is available in a remote data cache, a response with a completion indicator is provided to the requesting processor. The completion indicator allows the request to be met without having to probe local or remote nodes.

Abstract translation: 根据本发明，提供了用于提高多处理器，多集群系统中的数据访问效率的方法和装置。 允许各种事务在本地完成的机制通过提供与系统中的各种群集相关联的远程数据高速缓存来实现。 远程数据高速缓存接收远程集群中存储线路的数据和状态信息。 如果用于响应请求的信息在远程数据高速缓存中可用，则具有完成指示符的响应被提供给请求处理器。 完成指示器允许满足请求，而无需探测本地或远程节点。

公开(公告)号：WO2005003893A2

公开(公告)日：2005-01-13

申请号：PCT/US2004/019524

申请日：2004-06-18

Applicant: NEWISYS, INC. ,  KOTA, Rajesh ,  NEWAWARKER, Shashank ,  PRASADH, Guru ,  ZEITLER, Carl ,  GLASCO, David, B.

Inventor： KOTA, Rajesh ,  NEWAWARKER, Shashank ,  PRASADH, Guru ,  ZEITLER, Carl ,  GLASCO, David, B.

IPC: G06F

CPC classification number: G06F15/16

Abstract: According to the present invention, methods and apparatus are provided to allow dynamic multiple cluster system configuration changes. In one example, processors in the multiple cluster system share a virtual address space. Mechanisms for dynamically introducing and removing processors, I/O resources, and clusters are provided. The mechanisms can be implemented during reset or while a system is operating. Links can be dynamically enabled or disabled.

Abstract translation: 根据本发明，提供了用于允许动态多集群系统配置改变的方法和装置。 在一个示例中，多个集群系统中的处理器共享虚拟地址空间。 提供了动态引入和删除处理器，I / O资源和集群的机制。 这些机制可以在复位期间或系统运行时实现。 链接可以动态启用或禁用。

公开(公告)号：WO2004104794A2

公开(公告)日：2004-12-02

申请号：PCT/US2004/016111

申请日：2004-05-20

Applicant: NEWISYS, INC. ,  GLASCO, David, B.

Inventor： GLASCO, David, B.

IPC: G06F

CPC classification number: G06F12/0817

Abstract: According to the present invention, methods and apparatus are provided for increasing the efficiency of data access in a multiple processor, multiple cluster system. Mechanisms for allowing a variety of transactions to complete locally are implemented by providing remote data caches associated with the various clusters in the system. The remote data caches receive data and state information for memory lines held in remote clusters. State information is provided to the remote data cache using various mechanisms including a coherence directory and augmented source done messages.

Abstract translation: 根据本发明，提供了用于提高多处理器，多集群系统中的数据访问效率的方法和装置。 允许各种事务在本地完成的机制通过提供与系统中的各种群集相关联的远程数据高速缓存来实现。 远程数据高速缓存接收远程集群中存储线路的数据和状态信息。 使用包括相干目录和增强源完成消息的各种机制将状态信息提供给远程数据高速缓存。

公开(公告)号：WO2004092875A3

公开(公告)日：2004-10-28

申请号：PCT/US2004/010731

申请日：2004-04-08

Applicant: NEWISYS, INC. ,  ZEITLER, Carl ,  GLASCO, David, B. ,  KOTA, Rajesh ,  PRASADH, Guru ,  OEHLER, Richard, R. ,  EDRICH, David, S.

Inventor： ZEITLER, Carl ,  GLASCO, David, B. ,  KOTA, Rajesh ,  PRASADH, Guru ,  OEHLER, Richard, R. ,  EDRICH, David, S.

IPC: G06F12/00

Abstract: A computer system is described having a plurality of processing nodes interconnected by a first point-to-point architecture, and a system memory including a plurality of portions each of which is associated with one of the processing nodes. Each processing node includes a processor, and a memory controller for controlling acc4ess to the associated portion of the system memory, and may contain a host bridge for facilitating communication with a plurality of I/O devices. The first point-to-point architecture is operable to facilitate first transactions between the processors and the system memory. The computer system further includes at least one I/O controller and a second point-to-point architecture independent of the first point-to-point architecture and interconnecting the I/O controller and the host bridges. The at least one I/O controller is operable to facilitate second transactions between the I/O devices and the system memory via the second point-to-point architecture.