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    MULTI-CRYPTO-COLOR-GROUP VM/ENCLAVE MEMORY INTEGRITY METHOD AND APPARATUS
    2.
    发明申请
    MULTI-CRYPTO-COLOR-GROUP VM/ENCLAVE MEMORY INTEGRITY METHOD AND APPARATUS 审中-公开
    多色彩色群VM / ENCLAVE存储器完整性方法和装置

    公开(公告)号：WO2018063670A1

    公开(公告)日：2018-04-05

    申请号：PCT/US2017/049125

    申请日：2017-08-29

    Applicant: INTEL CORPORATION

    Inventor： DURHAM, David D. ,  CHHABRA, Siddhartha ,  DEUTSCH, Sergej ,  KOUNAVIS, Michael E. ,  NARENDRA TRIVEDI, Alpa T.

    IPC: G06F21/53 ,  G06F21/60 ,  G06F21/62

    CPC classification number: G06F12/1408 ,  G06F12/0831 ,  G06F12/12 ,  G06F12/128 ,  G06F12/1475 ,  G06F2212/1052 ,  G06F2212/621

    Abstract: Embodiments of apparatus, method, and storage medium associated with MCCG memory integrity for securing/protecting memory content/data of VM or enclave are described herein. In some embodiments, an apparatus may include one or more encryption engines to encrypt a unit of data to be stored in a memory in response to a write operation from a VM or an enclave of an application, prior to storing the unit of data into the memory in an encrypted form; wherein to encrypt the unit of data, the one or more encryption engines are to encrypt the unit of data using at least a key domain selector associated with the VM or enclave, and a tweak based on a color within a color group associated with the VM or enclave. Other embodiments may be described and/or claimed.

    Abstract translation: 这里描述了与用于保护/保护VM或飞地的存储器内容/数据的MCCG存储器完整性相关联的设备，方法和存储介质的实施例。 在一些实施例中，装置可以包括一个或多个加密引擎，用于在将数据单元存储到存储单元中之前，响应于来自VM或应用程序的飞地的写入操作来加密要存储在存储器中的数据单元 内存以加密形式; 其中为了加密所述数据单元，所述一个或多个加密引擎将使用与所述VM或飞地相关联的至少一个关键域选择器以及基于与所述VM相关联的颜色组内的颜色的调整来加密所述数据单元 或飞地。 其他实施例可以被描述和/或要求保护。

    METHOD, APPARATUS, AND SYSTEM FOR CACHE COHERENCY USING A COARSE DIRECTORY
    3.
    发明申请
    METHOD, APPARATUS, AND SYSTEM FOR CACHE COHERENCY USING A COARSE DIRECTORY 审中-公开
    用于使用粗略目录的高速缓存一致性的方法，装置和系统

    公开(公告)号：WO2017210143A1

    公开(公告)日：2017-12-07

    申请号：PCT/US2017/034889

    申请日：2017-05-28

    Applicant: INTEL CORPORATION

    Inventor： BLANKENSHIP, Robert G. ,  STEELY, Simon C. ,  SURY, Samantika S.

    IPC: G06F12/02

    CPC classification number: G06F3/0605 ,  G06F3/0625 ,  G06F3/0659 ,  G06F3/0673 ,  G06F12/0808 ,  G06F12/0811 ,  G06F12/0815 ,  G06F12/0824 ,  G06F12/0826 ,  G06F12/0831 ,  G06F12/0842 ,  G06F2212/1028 ,  G06F2212/1048 ,  Y02D10/13

    Abstract: Systems, methods, and apparatuses are directed to requesting access to a memory address; storing an identification of the memory address in a data structure; receiving a first request for access to the memory address, the request comprising a reference to a second processor core; storing the reference to the second processor in the data structure; receiving a second request for access to the memory address, the second request comprising a reference to a third processor core; determining, based on the data structure, that the third processor core is different from the second processor core; and responding to the second request without buffering the second request.

    Abstract translation: 系统，方法和设备涉及请求访问存储器地址; 将存储器地址的标识存储在数据结构中; 接收访问所述存储器地址的第一请求，所述请求包括对第二处理器核心的引用; 将对第二处理器的引用存储在数据结构中; 接收访问所述存储器地址的第二请求，所述第二请求包括对第三处理器核心的引用; 基于所述数据结构确定所述第三处理器核不同于所述第二处理器核; 并在不缓冲第二个请求的情况下响应第二个请求。

    CACHE MEMORY ACCESS
    4.
    发明申请
    CACHE MEMORY ACCESS 审中-公开
    高速缓存存取

    公开(公告)号：WO2017178925A1

    公开(公告)日：2017-10-19

    申请号：PCT/IB2017/051944

    申请日：2017-04-05

    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  IBM UNITED KINGDOM LIMITED ,  IBM (CHINA) INVESTMENT COMPANY LIMITED

    Inventor： WILLIAMS, Derek ,  GUTHRIE, Guy ,  JACKSON, Jonathan, Robert ,  STARKE, William ,  STUECHELI, Jeffrey

    IPC: G06F12/00

    CPC classification number: G06F12/0815 ,  G06F12/0811 ,  G06F12/0831 ,  G06F12/084 ,  G06F12/0842 ,  G06F12/0893 ,  G06F2212/1024 ,  G06F2212/6042 ,  G06F2212/621

    Abstract: A multiprocessor data processing system includes multiple vertical cache hierarchies supporting a plurality of processor cores, a system memory, and a system interconnect. In response to a load-and-reserve request from a first processor core, a first cache memory supporting the first processor core issues on the system interconnect a memory access request for a target cache line of the load-and-reserve request. Responsive to the memory access request and prior to receiving a system wide coherence response for the memory access request, the first cache memory receives from a second cache memory in a second vertical cache hierarchy by cache-to-cache intervention the target cache line and an early indication of the system wide coherence response for the memory access request. In response to the early indication and prior to receiving the system wide coherence response, the first cache memory initiating processing to update the target cache line in the first cache memory.

    Abstract translation: 多处理器数据处理系统包括支持多个处理器核的多个垂直高速缓存分层结构，系统存储器和系统互连。 响应于来自第一处理器核心的加载和保留请求，支持第一处理器核心的第一高速缓存存储器在系统互连上发出用于加载和保留请求的目标高速缓存行的存储器访问请求。 响应于存储器访问请求并且在接收对于存储器访问请求的系统范围的一致性响应之前，第一高速缓冲存储器通过高速缓存到高速缓存干预从第二垂直高速缓存层级中的第二高速缓冲存储器接收目标高速缓存行和 尽早指示存储器访问请求的系统范围内一致性响应。 响应于早期指示并且在接收系统范围一致性响应之前，第一高速缓冲存储器发起处理以更新第一高速缓冲存储器中的目标高速缓存行。

    MAINTAINING CACHE COHERENCY USING CONDITIONAL INTERVENTION AMONG MULTIPLE MASTER DEVICES
    5.
    发明申请
    MAINTAINING CACHE COHERENCY USING CONDITIONAL INTERVENTION AMONG MULTIPLE MASTER DEVICES 审中-公开
    使用多个主设备的条件干预维护高速缓存

    公开(公告)号：WO2017053087A1

    公开(公告)日：2017-03-30

    申请号：PCT/US2016/050987

    申请日：2016-09-09

    Applicant: QUALCOMM INCORPORATED

    Inventor： XU, Kun ,  TRUONG, Thuong, Quang ,  SUBRAMANIAM GANASAN, Jaya, Prakash ,  LE, Hien, Minh ,  RAMIREZ, Cesar, Aaron

    IPC: G06F12/0831

    CPC classification number: G06F12/0815 ,  G06F12/0831 ,  G06F2212/1024 ,  G06F2212/1028 ,  G06F2212/621 ,  Y02D10/13

    Abstract: Maintaining cache coherency using conditional intervention among multiple master devices is disclosed. In one aspect, a conditional intervention circuit is configured to receive intervention responses from multiple snooping master devices. To select a snooping master device to provide intervention data, the conditional intervention circuit determines how many snooping master devices have a cache line granule size the same as or larger than a requesting master device. If one snooping master device has a same or larger cache line granule size, that snooping master device is selected. If more than one snooping master device has a same or larger cache line granule size, a snooping master device is selected based on an alternate criteria. The intervention responses provided by the unselected snooping master devices are canceled by the conditional intervention circuit, and intervention data from the selected snooping master device is provided to the requesting master device.

    Abstract translation: 公开了使用多个主设备之间的条件干预来维护高速缓存一致性。 在一个方面，条件干预电路被配置为从多个窥探主设备接收干预响应。 为了选择窥探主设备来提供干预数据，条件干预电路确定有多少个窥探主设备具有与请求主设备相同或更大的高速缓存线粒度大小。 如果一个侦听主设备具有相同或更大的缓存线粒度大小，则选择该窥探主设备。 如果多个侦听主设备具有相同或更大的缓存线粒度大小，则会根据备用标准选择侦听主设备。 由未选择的窥探主设备提供的干预响应由条件干预电路取消，并且来自所选窥探主设备的干预数据被提供给请求主设备。

    高速缓存CACHE存储器系统及访问缓存行CACHE LINE的方法
    6.
    发明申请
    高速缓存CACHE存储器系统及访问缓存行CACHE LINE的方法 审中-公开

    公开(公告)号：WO2016082793A1

    公开(公告)日：2016-06-02

    申请号：PCT/CN2015/095795

    申请日：2015-11-27

    Applicant: 华为技术有限公司

    Inventor： 涂珍喜 ,  夏晶

    IPC: G06F12/08

    CPC classification number: G06F12/0846 ,  G06F12/0811 ,  G06F12/0831 ,  G06F12/084 ,  G06F2212/283 ,  G06F2212/314

    Abstract: 一种高速缓存cache存储器系统，该cache存储器系统包括多个上一级缓存和本级缓存，每个上一级缓存包括多个缓存行cache line，该本级缓存包括独占型标签随机接入存储器Exclusive Tag RAM和包容型标签随机接入存储器Inclusive Tag RAM，其中，该Exclusive Tag RAM用于优先存储每个上一级缓存中状态为修改独占UD的cache line的索引地址，该Inclusive Tag RAM用于存储每个上一级缓存中状态为独占UC、共享SC或修改共享SD的cache line的索引地址，由于该cache存储器系统采用Exclusive Tag RAM和Inclusive Tag RAM，一方面可以降低cache存储器系统中存储cache line的数据所需的容量，另一方面可以提高在cache存储器系统中获取cache line的数据的命中率，减少到主存中读取数据所造成的时延，提高了cache存储器系统的性能。

    INSTRUCTION AND LOGIC FOR MEMORY ACCESS IN A CLUSTERED WIDE-EXECUTION MACHINE
    8.
    发明申请
    INSTRUCTION AND LOGIC FOR MEMORY ACCESS IN A CLUSTERED WIDE-EXECUTION MACHINE 审中-公开
    集成式执行机器中的存储器访问的指令和逻辑

    公开(公告)号：WO2015097493A1

    公开(公告)日：2015-07-02

    申请号：PCT/IB2013/003071

    申请日：2013-12-23

    Applicant: INTEL CORPORATION

    Inventor： LECHENKO, Anton W ,  EFIMOV, Andrey ,  SHISHLOV, Sergey Y ,  IYER, Jayesh ,  BABAYAN, Boris A

    IPC: G06F12/08 ,  G06F12/12

    CPC classification number: G06F12/0842 ,  G06F9/3851 ,  G06F12/0804 ,  G06F12/0811 ,  G06F12/0831 ,  G06F12/0859 ,  G06F12/12 ,  G06F2212/1016 ,  G06F2212/1024 ,  G06F2212/6042 ,  G06F2212/621

    Abstract: A processor includes a Level-2 (L2) cache, a first and second cluster of execution units, and a first and second data cache unit (DCU) communicatively coupled to the respective clusters of execution units and to the L2 cache. The DCUs each include a data cache and logic to receive a memory operation from an execution unit, respond to the memory operation with information from the data cache when the information is available in the data cache, and retrieve the information from the L2 cache when the information is unavailable in the data cache. The processor further includes logic to maintain contents of the data cache of the first DCU as equal to contents of the data cache of the second DCU at all clock cycles of operation of the processor.

    Abstract translation: 处理器包括Level-2（L2）高速缓存，第一和第二执行单元簇，以及通信地耦合到相应的执行单元集群和L2高速缓存的第一和第二数据高速缓存单元（DCU）。 DCU各自包括数据高速缓存和用于从执行单元接收存储器操作的逻辑，当信息在数据高速缓存中可用时，利用来自数据高速缓存的信息来响应存储器操作，并且当第二高速缓存中的信息从 信息在数据高速缓存中不可用。 所述处理器还包括将所述第一DCU的数据高速缓存的内容保持为等于所述第二DCU的数据高速缓存的内容的逻辑，所述内容在所述处理器的操作的所有时钟周期中。

    MANAGING HIGH-CONFLICT CACHE LINES IN TRANSACTIONAL MEMORY COMPUTING ENVIRONMENTS
    9.
    发明申请
    MANAGING HIGH-CONFLICT CACHE LINES IN TRANSACTIONAL MEMORY COMPUTING ENVIRONMENTS 审中-公开
    在交易记忆计算环境中管理高冲突缓存行

    公开(公告)号：WO2015043979A1

    公开(公告)日：2015-04-02

    申请号：PCT/EP2014/069428

    申请日：2014-09-11

    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  IBM UNITED KINGDOM LIMITED

    Inventor： CAIN III, Harold, Wade ,  SHUM, Chung-Lung, Kevin ,  SCHWARZ, Eric, Mark ,  GSCHWIND, Michael, Karl ,  MICHAEL, Maged, Milad ,  SALAPURA, Valentina ,  BUSABA, Fadi, Yusuf

    IPC: G06F12/08

    CPC classification number: G06F12/0828 ,  G06F9/3004 ,  G06F9/30087 ,  G06F12/0831

    Abstract: Cache lines in a computing environment with transactional memory are configurable with a coherency mode. Cache lines in full-line coherency mode are operated or managed with full-line granularity. Cache lines in sub-line coherency mode are operated or managed as sub-cache line portions of a full cache line. When a transaction accessing a cache line in full-line coherency mode results in a transactional abort, the cache line may be placed in sub-line coherency mode if the cache line is a high-conflict cache line. The cache line may be associated with a counter in a conflict address detection table that is incremented whenever a transaction conflict is detected for the cache line. The cache line may be a high- conflict cache line when the counter satisfies a high-conflict criterion, such as reaching a threshold value. The cache line may be returned to full-line coherency mode when a reset criterion is satisfied.

    Abstract translation: 具有事务性存储器的计算环境中的高速缓存行可使用一致性模式进行配置。 全线一致性模式下的高速缓存行以全行粒度运行或管理。 子行一致性模式下的高速缓存行作为完整高速缓存行的子高速缓存行部分进行操作或管理。 当以全线一致性模式访问高速缓存行的事务导致事务中止时，如果高速缓存行是高冲突高速缓存行，则高速缓存行可以被置于子行一致性模式。 高速缓存行可以与冲突地址检测表中的计数器相关联，每当检测到高速缓存行的事务冲突时，它将递增。 当计数器满足诸如达到阈值的高冲突标准时，高速缓存行可以是高冲突高速缓存行。 当满足复位标准时，高速缓存行可以返回到全线一致性模式。

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