公开(公告)号：WO02078228A3

公开(公告)日：2003-07-31

申请号：PCT/RU0200120

申请日：2002-03-26

Applicant: ABROSIMOV IGOR ANATOLIEVICH

Inventor： ABROSIMOV IGOR ANATOLIEVICH ,  DEAS ALEXANDER ROGER

IPC: H04L25/02 ,  H04L7/00 ,  H04L7/02 ,  H04L7/033 ,  H04L25/14

CPC classification number: H04L7/0054 ,  H04L7/0037 ,  H04L7/0041 ,  H04L7/0045 ,  H04L7/033 ,  H04L25/14

Abstract: The present invention relates to the reduction of timing uncertainly in a high speed communications channel or interface. The receiver according to the invention comprises a plurality of samplers for latching data. The invention provides improvements to the Bit Error rate versus channel and inherent register noise, as a result of employment of the characteristic of phase noise within the receiving registers to measure the characteristics of the channel and to compensate for variations in the channel by altering the timing characteristics of the signal.

Abstract translation: 本发明涉及在高速通信信道或接口中不确定地减少时序。 根据本发明的接收机包括用于锁存数据的多个采样器。 本发明通过使用接收寄存器内的相位噪声的特性来测量信道的特性并且通过改变定时来补偿信道的变化，从而提供了比特误码率对信道和固有寄存器噪声的改进 信号的特点。

公开(公告)号：WO2003045003A1

公开(公告)日：2003-05-30

申请号：PCT/JP2002/012121

申请日：2002-11-20

Applicant: 株式会社アドバンテスト ,  碁石 優

Inventor： 碁石 優

IPC: H04L7/00

CPC classification number: G01R31/31922 ,  H03K5/135 ,  H04L7/0037 ,  H04L7/0041 ,  H04L7/0331

Abstract: A phase adjustment apparatus and a semiconductor test apparatus for automatically correcting irregularities of propagation delay of a transfer signal, so that the transfer signal transferred between apparatuses while synchronized with a high-speed clock can be received at a stable optimal timing at a reception side. The phase adjustment apparatus for transferring a transfer signal synchronized with a clock between a first apparatus of the transmission side and a second apparatus of the reception side includes phase adjustment means used when retiming the transfer signal with the clock of the reception side of the second apparatus. That is, the phase adjustment means corrects an unknown phase relationship between the clock of the reception side and the transfer signal and delays the transfer signal by a predetermined amount for adjustment so that the signal can be received with a stable retiming condition.

Abstract translation: 一种用于自动校正传送信号的传播延迟的不规则性的相位调整装置和半导体测试装置，从而可以在接收侧的稳定的最佳定时接收与高速时钟同步的装置之间传送的传送信号。 用于在发送侧的第一装置和接收侧的第二装置之间传送与时钟同步的传送信号的相位调整装置包括当与第二装置的接收侧的时钟重新定时传送信号时使用的相位调整装置 。 也就是说，相位调整装置校正接收侧的时钟与传送信号之间的未知相位关系，并且将传送信号延迟预定量以进行调整，使得可以以稳定的重新定时状态接收信号。

公开(公告)号：WO0171966A9

公开(公告)日：2003-02-06

申请号：PCT/US0140367

申请日：2001-03-20

Applicant: VITESSE SEMICONDUCTOR CORP

Inventor： MCCORMACK GARY D ,  TALAGA RONALD F JR

IPC: H04L25/40 ,  H03L7/099 ,  H03L7/10 ,  H04L7/00 ,  H04L7/02 ,  H04L7/033 ,  H04L25/02 ,  H04L25/06

CPC classification number: H04L7/033 ,  H03L7/0995 ,  H03L7/10 ,  H03L2207/14 ,  H04L7/0037 ,  H04L7/0334 ,  H04L25/0262 ,  H04L25/063

Abstract: A microprocessor (45) controlled data recovery unit with an adjustable sampling and signal comparison level. The data recovery unit includes a data channel (41a) and a monitor channel (41b). The monitor channel samples an incoming data stream in a varying manner. The results of the sampling in the monitor channel are used to adjust the sampling and comparing of the signal in the data channel. The data recovery unit includes a PLL based clock recovery unit (35) in one embodiment, and in another embodiment the clock signal is derived by the microprocessor.

Abstract translation: 微处理器（45）控制数据恢复单元具有可调取样和信号比较级别。 数据恢复单元包括数据通道（41a）和监视通道（41b）。 监视器通道以不同的方式对输入的数据流进行采样。 监视通道中采样的结果用于调整数据通道中信号的采样和比较。 在一个实施例中，数据恢复单元包括基于PLL的时钟恢复单元（35），在另一个实施例中，时钟信号由微处理器导出。

公开(公告)号：WO2002065688A1

公开(公告)日：2002-08-22

申请号：PCT/JP2001/001139

申请日：2001-02-16

Applicant: 富士通株式会社 ,  桑田直樹 ,  山本拓司

Inventor： 桑田直樹 ,  山本拓司

IPC: H04L7/033

CPC classification number: H03L7/10 ,  H03L7/081 ,  H03L7/085 ,  H03L7/089 ,  H03L7/091 ,  H04J3/0685 ,  H04L7/0037 ,  H04L7/033

Abstract: An improved timing extracting circuit of optical receiver, particularly using a frequency clock that is half the data transmission rate, and a duty shift adaptive circuit of optical transceiver. The timing extracting circuit has a detector circuit that, using a PLL circuit including a phase comparator circuit for performing a phase comparison between a data signal of a bit rate B (bit/s) and a clock signal of B/2 (Hz) at an interval of 2/B (sec), detects, in response to reception of a data signal of a predetermined pattern, that the phase comparator circuit no longer outputs any phase comparison information; and further has a control circuit responsive to that detection to control the phase of the clock signal so as to maintain the synchronization. The duty shift adaptive circuit controls, based on the result of determination of the duty between the input data before the synchronization of the PLL circuit is established and the input data after the establishment, the data identification phase before and after the establishment.

Abstract translation: 光接收机的改进的定时提取电路，特别是使用数据传输速率的一半的频率时钟，以及光收发器的占空比自适应电路。 定时提取电路具有检测电路，该电路使用包括相位比较器电路的PLL电路，用于在比特率B的数据信号（比特/秒）和时钟信号B / 2（Hz）之间进行相位比较 2 / B（sec）的间隔响应于接收到预定模式的数据信号而检测相位比较器电路不再输出任何相位比较信息; 并且还具有响应于该检测的控制电路来控制时钟信号的相位，以便保持同步。 占空比自适应电路基于确定PLL电路同步之前的输入数据与建立后的输入数据之间的占空比的确定结果来控制建立前后的数据识别阶段。

公开(公告)号：WO0002334A3

公开(公告)日：2000-04-27

申请号：PCT/US9911894

申请日：1999-05-28

Applicant: SUN MICROSYSTEMS INC

Inventor： DAVIDSON HOWARD L

IPC: G02B6/42 ,  H04B10/00 ,  H04J3/00 ,  H04J14/08 ,  H04L7/00 ,  H04L7/02 ,  H04L7/10 ,  H04L7/033

CPC classification number: H04L7/0075 ,  H04J14/08 ,  H04L7/0037 ,  H04L7/10

Abstract: An apparatus and method are provided for bit synchronization in an optical time division multiplexed communication system. The apparatus is couplable to an optical gate, such as an optical demultiplexer. The apparatus includes a programmable optical delay line couplable to an input clock; an optical synchronizer coupled to the programmable optical delay line and couplable to the optical gate; and a processor coupled to the programmable optical delay line and to the optical synchronizer. The processor includes program instructions to track bit synchronization between a clock pulse and a selected data bit during a communication session; and when a bit tracking range is approaching a predetermined limit, the processor has further instructions to interrupt the communication session, return the bit tracking range to a zero offset and correspondingly adjust a programmable delay, and resume the communication session.

Abstract translation: 提供了一种用于光时分复用通信系统中的比特同步的设备和方法。 该设备可耦合到光学门，例如光学解复用器。 该设备包括可耦合到输入时钟的可编程光学延迟线; 光学同步器，其耦合到所述可编程光学延迟线并且可耦合到所述光学门; 以及耦合到可编程光学延迟线和光学同步器的处理器。 处理器包括用于在通信会话期间跟踪时钟脉冲和所选数据比特之间的比特同步的程序指令; 并且当比特跟踪范围接近预定极限时，处理器还具有中断通信会话的指令，将比特跟踪范围返回到零偏移并相应地调整可编程延迟，并且恢复通信会话。

公开(公告)号：WO98049801A1

公开(公告)日：1998-11-05

申请号：PCT/DE1998/001015

申请日：1998-04-08

IPC: H04J3/06 ,  H04L7/033 ,  H04L7/04 ,  H04L25/04 ,  H04L25/06 ,  H04L1/20

CPC classification number: H04L7/048 ,  H04J3/0685 ,  H04L7/0037 ,  H04L7/033 ,  H04L25/063

Abstract: The invention relates to a method for regenerating data. According to the inventive method, protected data is transmitted and the error rate of the receiving signal (DS) is determined at the receiving end. The sampling instants and the decision threshold are varied within a predetermined range and the transmission errors detected during this process are used to set an optimum sampling instant (T,A) and an optimum decision threshold (O) in the (AB). Error correction ensures that additional transmission errors have no effect.

Abstract translation: 在用于保护数据的数据再生方法被发送。 在接收端，接收的信号（DS）的错误率被确定。 采样，以及判定阈值能够在预定的范围内变化，并且从所述，在此过程中，传输错误，最优采样时间（T，索引A）和在（AB）的最佳判定阈值（O）设置确定。 由于纠错，额外的传输错误没有影响。

公开(公告)号：WO1994026032A1

公开(公告)日：1994-11-10

申请号：PCT/SE1994000268

申请日：1994-03-24

Applicant: TELEFONAKTIEBOLAGET LM ERICSSON

Inventor： TELEFONAKTIEBOLAGET LM ERICSSON ,  LIEDBERG, Nils, Per, Åke

IPC: H03L07/081

CPC classification number: H03L7/081 ,  H04J3/0688 ,  H04L7/0037 ,  Y10S331/02

Abstract: According to the present invention, an unlimited number of steps or increments of given size are obtained in a delay line for phase alignment of, for instance, the signal from a crystal oscillator (XO) by momentarily switching between two parallel delay lines. One delay line operates as an active or enabled delay line while the other line is disabled or inactive. It is ensured at the same time that the inactive delay line produces a signal which has the same relative phase as the active delay line, this absolute phase differing by N x 2 pi , where N is a positive or a negative integer other than zero. The inventive method and the inventive device enable the active delay line to operate constantly within its regulation range and the phase of the local oscillator can be kept continuously locked to the phase of the reference signal. The inventive device also includes an oscillator (2), a phase comparator (5) and counter logic (4) and a further phase comparator (7) and a selection circuit (6) for signal selection from that one of the two parallel delay lines (10, 11) that has been placed in its active mode.

Abstract translation: 根据本发明，在用于通过在两个并行延迟线之间暂时切换来自晶体振荡器（XO）的信号的相位对准的延迟线中获得给定尺寸的无限数量的步长或增量。 一个延迟线作为有效或有效的延迟线工作，而另一条线路被禁用或无效。 确保在不活动延迟线产生具有与有效延迟线相同的相位相位的信号的同时，该绝对相位相差N×2π，其中N是除零之外的正整数或负整数。 本发明的方法和本发明的器件使得有源延迟线能够在其调节范围内恒定地操作，并且可以将本地振荡器的相位保持连续锁定到参考信号的相位。 本发明的装置还包括振荡器（2），相位比较器（5）和计数器逻辑（4）以及另外的相位比较器（7）和选择电路（6），用于从两个并行延迟线 （10,11）已被置于其活动模式。

公开(公告)号：WO2018070190A1

公开(公告)日：2018-04-19

申请号：PCT/JP2017/033635

申请日：2017-09-19

Applicant: オムロン株式会社

Inventor： 福田　泰士 ,  江口　重行

IPC: G05B19/05 ,  H04L12/28

CPC classification number: H04L7/0037 ,  G05B19/05 ,  G06F17/5054 ,  H04L7/0008 ,  H04L12/28

Abstract: 制御システムを構成する演算装置が提供される。演算装置は、制御システムにおける時刻を管理するマスタクロックと、第１の通信線を介して第１の機能ユニットとの間でデータを送受信する第１の通信回路と、第２の通信線を介して第２の機能ユニットとの間でデータを送受信する第２の通信回路と、第１の機能ユニットにおいて受信された出力データに対応する信号を出力するための処理を開始すべき第１のタイミングを第１の機能ユニットへ指示するとともに、第２の機能ユニットにおいて受信された出力データに対応する信号を出力するための処理を開始すべき第２のタイミングを第２の機能ユニットへ指示する、タイミング指示手段とを含む。

Abstract translation: 构成控制系统的运算单元被提供。 通过一个主时钟运算装置用于在控制系统中管理的时间，用于发送和经由第一通信线路的第一功能单元之间发送和接收数据，所述第二通信线路的第一通信电路 第二通信电路，所述第一定时开始处理，用于输出对应于用于数据发送和接收到和从所述第二功能单元碲在第一功能单元所接收的输出数据的信号 指示给第一功能单元，指示第二定时过程应该用于输出对应于在所述第二功能单元接收到所述第二功能单元的输出数据的信号被启动， 和时间指示手段。

公开(公告)号：WO2016196848A1

公开(公告)日：2016-12-08

申请号：PCT/US2016/035598

申请日：2016-06-02

Applicant: MARVELL WORLD TRADE LTD.

Inventor： ZHANG, Tao ,  LIU, Xuemei ,  WANG, Hui

IPC: H03L7/081 ,  H03K5/13

CPC classification number: H03L7/0807 ,  H03K5/06 ,  H03L7/0814 ,  H03L7/091 ,  H04L7/0037 ,  H04L7/0337

Abstract: A programmable delay line comprises a delay stage responsive to an analog control signal and responsive to one or more digital control signals. The delay stage generates an output signal that is delayed relative to an input signal by a delay amount. The delay amount controlled by a value of the analog control signal and one or more values of the digital control signals. A method for controlling a delay locked loop circuit comprises providing, to a programmable delay line of the delay locked loop circuit, a one or more digital signals, and providing, to the programmable delay line, an analog signal. A first portion of a delay produced by the programmable delay line corresponds to values of the one or more digital signals. A second portion of the delay produced by the programmable delay line corresponds to a value of the analog signal.

Abstract translation: 可编程延迟线包括响应于模拟控制信号并响应于一个或多个数字控制信号的延迟级。 延迟级产生相对于输入信号延迟延迟量的输出信号。 延迟量由模拟控制信号的值和数字控制信号的一个或多个值控制。 一种用于控制延迟锁定环电路的方法包括：向可延迟锁定环电路的可编程延迟线提供一个或多个数字信号，并向可编程延迟线提供模拟信号。 由可编程延迟线产生的延迟的第一部分对应于一个或多个数字信号的值。 由可编程延迟线产生的延迟的第二部分对应于模拟信号的值。

公开(公告)号：WO2016173741A1

公开(公告)日：2016-11-03

申请号：PCT/EP2016/054217

申请日：2016-02-29

Applicant: ABB TECHNOLOGY AG

Inventor： DZUNG, Dacfey ,  LOEKSTAD, Trond

IPC: H04J3/06

CPC classification number: H04L7/0037 ,  H04J3/0667 ,  H04L67/42

Abstract: The present invention is directed towards a method, a system, and a device which allow an improved synchronization of a system-wide timing information over a network. Hence, slave clocks can be synchronized to a high quality clock, such as a master clock.

Abstract translation: 本发明涉及一种允许通过网络改进系统范围定时信息同步的方法，系统和装置。 因此，从时钟可以与高质量时钟同步，例如主时钟。