公开(公告)号：WO2005064479A3

公开(公告)日：2006-06-15

申请号：PCT/US2004040137

申请日：2004-12-01

Applicant: INTEL CORP ,  COULSON RICHARD ,  ROYER ROBERT JR ,  LEETE BRIAN

Inventor： COULSON RICHARD ,  ROYER ROBERT JR ,  LEETE BRIAN

IPC: G06F1/32 ,  G06F1/26 ,  G06F3/06 ,  G06F12/08

CPC classification number: G06F1/3275 ,  G06F1/263 ,  G06F1/3203 ,  G06F12/0804 ,  G06F12/0862 ,  G06F12/0866 ,  G06F2212/1028 ,  Y02D10/13 ,  Y02D10/14

Abstract: Briefly, in accordance with an embodiment of the invention, a system and method to alter a cache policy of the system in response to the system transitioning from a first power state to a second power state is provided. The system may include a non-volatile disk cache and a disk memory, wherein the cache policy is used by the non-volatile disk cache to cache information for the disk memory.

Abstract translation: 简而言之，根据本发明的实施例，提供了一种系统和方法，用于响应于系统从第一功率状态转换到第二功率状态而改变系统的高速缓存策略。 系统可以包括非易失性磁盘高速缓存和磁盘存储器，其中高速缓存策略被非易失性磁盘高速缓存用于缓存磁盘存储器的信息。

公开(公告)号：WO2005066772A3

公开(公告)日：2006-04-27

申请号：PCT/US2004039481

申请日：2004-11-24

Applicant: INTEL CORP ,  BRANNOCK KIRK ,  GARNEY JOHN ,  COULSON RICHARD

Inventor： BRANNOCK KIRK ,  GARNEY JOHN ,  COULSON RICHARD

IPC: G06F9/445

CPC classification number: G06F9/4403 ,  G06F8/60

Abstract: Briefly, in accordance with an embodiment of the invention, an apparatus and method to store initialization and configuration information is provided. The method may include storing basic input/output system (BIOS) software in a polymer memory. The method may further include copying a first portion of the BIOS software from the polymer memory to a random access memory (RAM) buffer of a memory controller, wherein the RAM buffer has a storage capacity of at least about two kilobytes (KB).

Abstract translation: 简而言之，根据本发明的实施例，提供了一种用于存储初始化和配置信息的装置和方法。 该方法可以包括将基本输入/输出系统（BIOS）软件存储在聚合物存储器中。 该方法还可以包括将BIOS软件的第一部分从聚合物存储器复制到存储器控制器的随机存取存储器（RAM）缓冲器，其中RAM缓冲器具有至少约两千字节（KB）的存储容量。

公开(公告)号：WO2005064479A2

公开(公告)日：2005-07-14

申请号：PCT/US2004/040137

申请日：2004-12-01

Applicant: INTEL CORPORATION ,  COULSON, Richard ,  ROYER, Robert, Jr. ,  LEETE, Brian

Inventor： COULSON, Richard ,  ROYER, Robert, Jr. ,  LEETE, Brian

IPC: G06F12/08

CPC classification number: G06F1/3275 ,  G06F1/263 ,  G06F1/3203 ,  G06F12/0804 ,  G06F12/0862 ,  G06F12/0866 ,  G06F2212/1028 ,  Y02D10/13 ,  Y02D10/14

Abstract: Briefly, in accordance with an embodiment of the invention, a system and method to alter a cache policy of the system in response to the system transitioning from a first power state to a second power state is provided. The system may include a non-volatile disk cache and a disk memory, wherein the cache policy is used by the non-volatile disk cache to cache information for the disk memory.

Abstract translation: 简而言之，根据本发明的实施例，提供了一种系统和方法，用于响应于系统从第一功率状态转换到第二功率状态而改变系统的高速缓存策略。 该系统可以包括非易失性磁盘高速缓存和磁盘存储器，其中高速缓存策略由非易失性磁盘高速缓存用于缓存磁盘存储器的信息。

公开(公告)号：WO2003001380A2

公开(公告)日：2003-01-03

申请号：PCT/US2002/018174

申请日：2002-06-07

Applicant: INTEL CORPORATION ,  GARNEY, John, I. ,  COULSON, Richard ,  FABER, Robert, W.

Inventor： GARNEY, John, I. ,  COULSON, Richard ,  FABER, Robert, W.

IPC: G06F11/00

CPC classification number: G11C29/44

Abstract: One aspect of the invention provides a novel scheme to preserve the failure state of a memory location. According to one embodiment, the data is read from a memory location in a read-destructive memory device. If the data is found to be valid (uncorrupted) it is written back to the memory location from where it was read in order to preserve it. If the data is found to be invalid (corrupted) then a failure codeword is written in the memory location to indicate a failure of the memory location. The failure codeword may be preselected or dynamically calculated so that it has a mathematical distance greater than all correctable data patterns.

Abstract translation: 本发明的一个方面提供了一种保存存储器位置的故障状态的新方案。 根据一个实施例，从读破坏性存储器件中的存储器位置读取数据。 如果数据被发现是有效的（未破坏的），它将被写回到它被读取的存储器位置，以便保留它。 如果发现数据无效（损坏），则故障码字被写入存储器位置以指示存储器位置的故障。 可以预先选择或动态地计算故障代码字，使其具有大于所有可校正数据模式的数学距离。

公开(公告)号：WO0201365A3

公开(公告)日：2002-04-11

申请号：PCT/US0117851

申请日：2001-06-01

Applicant: INTEL CORP ,  COULSON RICHARD

Inventor： COULSON RICHARD

IPC: G06F3/06 ,  G06F12/08

CPC classification number: G06F12/0873 ,  G06F12/0893 ,  G06F2212/214 ,  G06F2212/313

Abstract: A non-volatile cache including a non-volatile memory to cache data that is stored on a mass storage device.

Abstract translation: 包含非易失性存储器的非易失性高速缓存以高速缓存存储在大容量存储设备上的数据。