公开(公告)号：WO2015099730A1

公开(公告)日：2015-07-02

申请号：PCT/US2013/077785

申请日：2013-12-26

Applicant: INTEL CORPORATION ,  DAS SHARMA, Debendra ,  BLANKENSHIP, Robert G. ,  CHITTOR, Suresh S. ,  CRETA, Kenneth C. ,  FLEISCHER, Balint ,  JEN, Michelle C. ,  KUMAR, Mohan J. ,  MORRIS, Brian S.

Inventor： DAS SHARMA, Debendra ,  BLANKENSHIP, Robert G. ,  CHITTOR, Suresh S. ,  CRETA, Kenneth C. ,  FLEISCHER, Balint ,  JEN, Michelle C. ,  KUMAR, Mohan J. ,  MORRIS, Brian S.

IPC: G06F13/14 ,  G06F13/20 ,  G06F12/00

CPC classification number: G06F13/1663 ,  G06F12/1475 ,  G06F13/385 ,  G06F13/4282 ,  G06F2212/1052 ,  G06F2213/0026 ,  Y02D10/14 ,  Y02D10/151

Abstract: A shared memory controller is to service load and store operations received, over data links, from a plurality of independent nodes to provide access to a shared memory resource. Each of the plurality of independent nodes is to be permitted to access a respective portion of the shared memory resource. Interconnect protocol data and memory access protocol data are sent on the data links and transitions between the interconnect protocol data and memory access protocol data can be defined and identified.

Abstract translation: 共享存储器控制器是通过数据链路从多个独立节点服务加载和存储从数据链路接收的操作，以提供对共享存储器资源的访问。 要允许多个独立节点中的每一个访问共享存储器资源的相应部分。 在数据链路上发送互连协议数据和存储器访问协议数据，并且可以定义和识别互连协议数据和存储器访问协议数据之间的转换。

公开(公告)号：WO2015099719A1

公开(公告)日：2015-07-02

申请号：PCT/US2013/077744

申请日：2013-12-26

Applicant: INTEL CORPORATION ,  WU, Zuoguo J. ,  WAGH, Mahesh ,  DAS SHARMA, Debendra ,  PASDAST, Gerald S. ,  AYYASAMY, Ananthan ,  LI, Xiaobei ,  BLANKENSHIP, Robert G. ,  SAFRANEK, Robert J.

Inventor： WU, Zuoguo J. ,  WAGH, Mahesh ,  DAS SHARMA, Debendra ,  PASDAST, Gerald S. ,  AYYASAMY, Ananthan ,  LI, Xiaobei ,  BLANKENSHIP, Robert G. ,  SAFRANEK, Robert J.

IPC: G06F13/14 ,  G06F13/38

CPC classification number: G06F13/4282 ,  G06F13/124 ,  G06F13/4273 ,  G06F15/173 ,  Y02D10/14 ,  Y02D10/151

Abstract: Physical layer logic is provided that is to receive data on one or more data lanes of a physical link, receive a valid signal on another of the lanes of the physical link identifying that valid data is to follow assertion of the valid signal on the one or more data lanes, and receive a stream signal on another of the lanes of the physical link identifying a type of the data on the one or more data lanes.

Abstract translation: 提供物理层逻辑，其是在物理链路的一个或多个数据通道上接收数据，在物理链路的另一个通道上接收一个有效信号，该有效信号标识该有效数据将跟随有效信号在一个或 更多的数据通道，并且在物理链路的另一个通道上接收标识在一个或多个数据通道上的数据类型的流信号。

公开(公告)号：WO2014065876A9

公开(公告)日：2014-05-01

申请号：PCT/US2013/032670

申请日：2013-03-15

Applicant: INTEL CORPORATION ,  BEERS, Robert ,  BLANKENSHIP, Robert G. ,  SAFRANEK, Robert, J. ,  WILLEY, Jeff ,  MADDOX, Robert A. ,  SPINK, Aaron T.

Inventor： BEERS, Robert ,  BLANKENSHIP, Robert G. ,  SAFRANEK, Robert, J. ,  WILLEY, Jeff ,  MADDOX, Robert A. ,  SPINK, Aaron T.

IPC: G06F13/42 ,  G06F13/14

Abstract: A coherence protocol message is sent corresponding to a particular cache line. A potential conflict involving the particular cache line is identified and a forward request is sent to a home agent to identify the potential conflict. A forward response can be received in response to the forward request from the home agent and a response to the conflict can be determined

公开(公告)号：WO2013103339A1

公开(公告)日：2013-07-11

申请号：PCT/US2012/020175

申请日：2012-01-04

Applicant: INTEL CORPORATION ,  CRETA, Kenneth C. ,  HORIHAN, Jason W. ,  BLANKENSHIP, Robert G. ,  CHENG, Kai

Inventor： CRETA, Kenneth C. ,  HORIHAN, Jason W. ,  BLANKENSHIP, Robert G. ,  CHENG, Kai

IPC: G06F13/14 ,  G06F12/00 ,  G06F15/80

CPC classification number: G06F3/0659 ,  G06F3/061 ,  G06F3/0679 ,  G06F13/16 ,  G06F13/4234 ,  G06F2206/1014 ,  G11C13/0002 ,  G11C14/009

Abstract: Methods and apparatus relating to provide bimodal functionality between a coherent link and memory expansion are described. In one embodiment, a processor is coupled to one or more agents via a coherent interconnect. The processor is also coupled to one or more Dual Inline Memory Modules (DIMMs) via a link logic. The logic supports read or write commands directed at the one or more DIMMs based on a single bit of data. Other embodiments are also disclosed and claimed.

Abstract translation: 描述了在相干链路和存储器扩展之间提供双模功能相关的方法和装置。 在一个实施例中，处理器经由相干互连耦合到一个或多个代理。 处理器还通过链路逻辑耦合到一个或多个双列直插内存模块（DIMM）。 该逻辑支持基于单个数据位读取或写入指向一个或多个DIMM的命令。 还公开并要求保护其他实施例。