公开(公告)号：WO2018231526A1

公开(公告)日：2018-12-20

申请号：PCT/US2018/035167

申请日：2018-05-30

Applicant: QUALCOMM INCORPORATED

Inventor： WIETFELDT, Richard Dominic ,  MISHRA, Lalan Jee

IPC: G06F13/38 ,  G06F13/42 ,  G06F15/163 ,  G06F15/17

CPC classification number: H04L12/5601 ,  G06F13/385 ,  G06F13/4282 ,  G06F21/606 ,  G06F21/85 ,  H04L5/0044 ,  H04L49/3081 ,  H04L63/0428 ,  H04L2012/563

Abstract: In an aspect, an apparatus obtains a payload to be transmitted to a receiver device, obtains a virtual general-purpose input/output and messaging interface (VGMI) packet that includes at least the payload, a virtual channel identifier, and a function bit configured as a virtual channel marker bit to indicate that the VGMI packet includes the virtual channel identifier, wherein the virtual channel identifier indicates information associated with processing the payload, and transmits the VGMI packet to the receiver device. In another aspect, an apparatus receives a VGMI packet from a transmitter device, wherein the VGMI packet includes at least a payload and a virtual channel identifier, determines that the VGMI packet includes the virtual channel identifier based on a function bit configured as a virtual channel marker bit, wherein the virtual channel identifier indicates information associated with processing the payload, and processes the data based on the information.

公开(公告)号：WO2018140045A1

公开(公告)日：2018-08-02

申请号：PCT/US2017/015523

申请日：2017-01-28

Applicant: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.

Inventor： SEILER, Peter ,  BARTH, Justin ,  LESSMAN, Mark

IPC: G06F1/16 ,  G06F13/38

CPC classification number: G06F13/385 ,  G06F13/38

Abstract: An adaptable connector, a non-standard PCIe module, and a computer readable medium are disclosed. The adaptable connector for a PCIe interface allows for multiple standard PCIe modules and non-standard PCIe modules at different times An external I/O port has a set of non-PCIe I/O signal lanes coupled to the adaptable connector in lieu of a set of root port host PCIe signal lanes when a non-standard PCIe module is mated to the adaptable connector.

公开(公告)号：WO2017172166A1

公开(公告)日：2017-10-05

申请号：PCT/US2017/019729

申请日：2017-02-27

Applicant: VIEWPOST IP HOLDINGS, LLC

Inventor： PIERSON, Christopher ,  MCCORMACK, Andrew

IPC: B60T7/12 ,  G05D1/00 ,  G06F7/00 ,  G06F17/00

CPC classification number: G06F11/3055 ,  G06F11/3027 ,  G06F11/3048 ,  G06F11/3051 ,  G06F13/385 ,  G06F13/4072 ,  G06F13/4282

Abstract: Systems and methods are presented for detecting, by a universal serial bus (USB) drive operatively coupled with a computing device, power from the computing device, and determining, by the USB drive, that drivers associated with the USB drive have been installed on the computing device. The systems and methods may determine that drivers associated with the USB drive have been installed by sending a digital signal indicating a predetermined keystroke until the USB drive receives a response from the computing device, and receiving, from the computing device, a feedback response to the digital signal indicating the predetermined keystroke has been received. The systems and methods further executing, by the USB drive, a macro to download a payload to the computing device, causing by the USB drive, the payload to execute on the computing device, and causing, by the USB drive, the downloaded payload to be deleted from the computing device.

Abstract translation: 提出了系统和方法，用于通过与计算设备可操作地耦合的通用串行总线（USB）驱动器检测来自计算设备的电力，并且由USB驱动器确定与 USB驱动器已安装在计算设备上。 系统和方法可以通过发送指示预定击键的数字信号来确定已经安装了与USB驱动器相关联的驱动器，直到USB驱动器从计算设备接收到响应，并且从计算设备接收对 指示已经接收到预定击键的数字信号。 所述系统和方法进一步由所述USB驱动器执行宏以将有效载荷下载到所述计算设备，由所述USB驱动器使所述有效载荷在所述计算设备上执行，并且由所述USB驱动器使所下载的有效载荷 从计算设备中删除。

公开(公告)号：WO2017172014A1

公开(公告)日：2017-10-05

申请号：PCT/US2017/015545

申请日：2017-01-30

Applicant: INTEL CORPORATION

Inventor： SRIVASTAVA, Amit Kumar

IPC: G06F13/38

CPC classification number: G06F13/4295 ,  G06F13/385 ,  G06F13/4022

Abstract: An example system for side band communication can include a processor, a system-on-chip (SOC), and a repeater communicatively coupled to the processor and the SOC. The repeater can receive packets from a first transceiver. The repeater can also detect a pattern in the packets to identify a guest protocol. The repeater can further send the packets from the first transceiver to the SOC via a second transceiver based on the identified guest protocol.

Abstract translation: 用于边带通信的示例系统可以包括处理器，片上系统（SOC）以及通信地耦合到处理器和SOC的中继器。 中继器可以接收来自第一收发器的分组。 中继器还可以检测数据包中的模式以识别访客协议。 基于识别的访客协议，中继器可以进一步经由第二收发器将来自第一收发器的分组发送到SOC。

公开(公告)号：WO2017091205A1

公开(公告)日：2017-06-01

申请号：PCT/US2015/062280

申请日：2015-11-24

Applicant: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.

Inventor： SIMPSON, Shell S. ,  BLAIR, Timothy P.

IPC: G06F13/14

CPC classification number: G06F13/14 ,  G06F13/385

Abstract: Examples disclosed herein relate to capturing a first machine-readable link via an image capture device, retrieving a first content element associated with the first machine-readable link, determining whether the first content element is related to a second content element associated with a second machine-readable link, and in response to determining that the first content element is related to the second content element associated with a second machine-readable link, retrieving the second content element.

Abstract translation: 这里公开的示例涉及经由图像捕获设备捕获第一机器可读链接，检索与第一机器可读链接相关联的第一内容元素，确定第一内容元素是否与 第二内容元素与第二机器可读链接相关联，并且响应于确定第一内容元素与与第二机器可读链接相关联的第二内容元素相关，检索第二内容元素。

公开(公告)号：WO2016194631A1

公开(公告)日：2016-12-08

申请号：PCT/JP2016/064888

申请日：2016-05-19

Applicant: ソニー株式会社

Inventor： 石川　裕也

IPC: G06F3/00 ,  G06F1/26 ,  G06F13/10

CPC classification number: G11C5/14 ,  G06F1/26 ,  G06F3/00 ,  G06F13/10 ,  G06F13/385 ,  G11C7/00

Abstract: 本開示の電子機器は、複数のポートを有する集線部と、複数のポートのうち、ホストとして動作する機器が接続されるホストポートを、ホストポートに接続された第１の機器から供給された切替指示に基づいて切り替える制御部とを備える。

Abstract translation: 本公开的电子设备具有：具有多个端口的线路集中器单元;以及控制单元，用于根据从连接到主机端口的第一设备提供的切换命令来执行主机端口切换，所述主机端口为 多个端口中的一个连接作为主机设备的设备。

公开(公告)号：WO2016178761A1

公开(公告)日：2016-11-10

申请号：PCT/US2016/025477

申请日：2016-04-01

Applicant: QUALCOMM INCORPORATED

Inventor： GERBER, Nir ,  AMARILIO, Lior ,  GIL, Amit

IPC: G06F1/32

CPC classification number: G06F1/3253 ,  G06F13/385 ,  G06F2213/0042 ,  Y02D10/151

Abstract: Aspects disclosed in the detailed description include scheduled universal serial bus (USB) low-power operations. In this regard, in one aspect, a USB host controller determines a low-power operation schedule for a USB client device. The low-power operation schedule comprises one or more scheduled low-power operation periods, each corresponding to a respective entry time and a respective exit time. The USB host controller communicates the low-power operation schedule to the USB client device using one or more USB standard packets. By scheduling the one or more scheduled low-power operation periods with respective entry and exit times, the USB host controller or the USB client controller is able to start and end the one or more scheduled low-power operation periods without incurring additional signaling, thus improving efficiency of the USB low-power operation. Further, by communicating the low-power operation schedule using USB standard packets, it is possible to preserve compatibility with USB standards.

Abstract translation: 在详细描述中公开的方面包括调度的通用串行总线（USB）低功率操作。 在这方面，在一方面，USB主机控制器确定USB客户端设备的低功率操作调度。 低功率操作调度包括一个或多个调度的低功率操作周期，每个周期对应于相应的进入时间和相应的退出时间。 USB主机控制器使用一个或多个USB标准数据包将低功耗操作计划传送到USB客户端设备。 通过调度具有相应进入和退出时间的一个或多个调度的低功率操作时段，USB主机控制器或USB客户端控制器能够开始和结束一个或多个调度的低功率操作时段，而不会产生额外的信号，因此 提高USB低功耗操作的效率。 此外，通过使用USB标准分组传送低功率运行调度表，可以保持与USB标准的兼容性。

公开(公告)号：WO2016149086A3

公开(公告)日：2016-11-03

申请号：PCT/US2016021977

申请日：2016-03-11

Applicant: MICROCHIP TECH INC

Inventor： KRIS BRYAN ,  WOJEWODA IGOR ,  CATHERWOOD MIKE ,  FALL BRIAN ,  TOLLEFSON JASON ,  PEPPING JIM ,  MICKEY DAVE ,  SPOHRER THOMAS ,  DUMAIS ALEX ,  WILKIE CALUM ,  SHEARD VINCENT

IPC: G06F15/167 ,  G06F1/22 ,  G06F13/38

CPC classification number: G06F13/4282 ,  G06F1/22 ,  G06F13/1673 ,  G06F13/364 ,  G06F13/385 ,  G06F15/167 ,  Y02D10/14 ,  Y02D10/151

Abstract: A microcontroller device has a housing with a plurality of external pins. a first microcontroller with a first central processing unit (CPU), a first system bus coupled with the first CPU, first memory coupled with the first system bus, and a first plurality of peripheral devices coupled with the first system bus, and a second microcontroller with a second central processing unit (CPU), a second system bus coupled with the second CPU, second memory coupled with the second system bus, and a second plurality of peripheral devices coupled with the second system bus, wherein first and second microcontroller communicate only via a dedicated interface.

Abstract translation: 微控制器装置具有带有多个外部引脚的外壳。 具有第一中央处理单元（CPU）的第一微控制器，与第一CPU耦合的第一系统总线，与第一系统总线耦合的第一存储器以及与第一系统总线耦合的第一多个外围设备，以及第二微控制器 与第二中央处理单元（CPU），与第二CPU耦合的第二系统总线，与第二系统总线耦合的第二存储器以及与第二系统总线耦合的第二多个外围设备，其中第一与第二微控制器仅通信 通过专用接口。

公开(公告)号：WO2016149078A3

公开(公告)日：2016-11-03

申请号：PCT/US2016021962

申请日：2016-03-11

Applicant: MICROCHIP TECH INC

Inventor： KRIS BRYAN ,  WOJEWODA IGOR ,  CATHERWOOD MIKE ,  FALL BRIAN ,  TOLLEFSON JASON ,  WILKIE CALUM ,  MICKEY DAVE ,  SPOHRER THOMAS ,  DUMAIS ALEX

IPC: G06F15/78 ,  G06F13/38

CPC classification number: G06F13/4282 ,  G06F13/1673 ,  G06F13/364 ,  G06F13/385 ,  G06F15/7807 ,  Y02D10/12 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D10/151

Abstract: A microcontroller device has a housing with a plurality of external pins having a plurality of input/output pins, a first microcontroller with a first central processing unit (CPU), a first system bus coupled with the first CPU, first memory coupled with the first system bus, and a first plurality of peripheral devices coupled with the first system bus, a second microcontroller with a second central processing unit (CPU), a second system bus coupled with the second CPU, second memory coupled with the second system bus, and a second plurality of peripheral devices coupled with the second system bus, and a pad ownership multiplexer unit being controllable to assign control of the input/output pins to either the first microcontroller or the second microcontroller, wherein the number of external pins is less than the sum of a data bus width of the first and second microcontroller.

Abstract translation: 微控制器装置具有壳体，多个外部引脚具有多个输入/输出引脚，具有第一中央处理单元（CPU）的第一微控制器，与第一CPU耦合的第一系统总线，与第一中央处理单元 系统总线和与第一系统总线耦合的第一多个外围设备，具有第二中央处理单元（CPU）的第二微控制器，与第二CPU耦合的第二系统总线，与第二系统总线耦合的第二存储器，以及 与第二系统总线耦合的第二多个外围设备，以及焊盘所有权复用器单元，其可控制以将输入/输出引脚的控制分配给第一微控制器或第二微控制器，其中外部引脚的数量小于 第一和第二微控制器的数据总线宽度之和。

公开(公告)号：WO2016172634A1

公开(公告)日：2016-10-27

申请号：PCT/US2016/029056

申请日：2016-04-22

Applicant: INTERNATIONAL MICROSYSTEMS, INC.

Inventor： SCHADE, Peter, A.

IPC: H04L12/28

CPC classification number: G06F15/17362 ,  G06F13/28 ,  G06F13/385 ,  G06F13/4221 ,  G06F15/161 ,  G06F15/17

Abstract: A hierarchical array computer architecture comprised of a master computer connected to a plurality of node computers wherein each node has a memory segment. A high speed connection scheme between the master computer and the nodes allows the master computer or individual nodes conditional access to the node memory segments. The resulting architecture creates an array computer with a large distributed memory in which each memory segment of the distributed memory has an associated computing element; the entire array being housed in a blade server type enclosure. The array computer created with this architecture provides a linear increase of processing speed corresponding to the number of nodes.

Abstract translation: 一种分层阵列计算机架构，包括连接到多个节点计算机的主计算机，其中每个节点具有存储器段。 主计算机和节点之间的高速连接方案允许主计算机或各个节点有条件地访问节点存储器段。 所得到的架构创建具有大分布式存储器的阵列计算机，其中分布式存储器的每个存储器段具有相关联的计算元件; 整个阵列容纳在刀片服务器型机箱中。 使用此架构创建的阵列计算机提供了对应于节点数量的处理速度的线性增加。