公开(公告)号：WO2011154780A1

公开(公告)日：2011-12-15

申请号：PCT/IB2010/052617

申请日：2010-06-11

Applicant: FREESCALE SEMICONDUCTOR, INC. ,  CLOETENS, Henri

Inventor： CLOETENS, Henri

IPC: G06F21/24 ,  G06F11/10 ,  G06F12/00

CPC classification number: G06F11/1028 ,  G06F21/64 ,  G06F21/79

Abstract: A method (400) for providing data protection for data stored within a Random Access Memory (RAM) element. The method comprises receiving data to be written to memory (420), dividing the received data into a plurality of data sections (430), applying error correction codes to the data sections to form codeword sections (440), interleaving the codeword sections to form an interleaved data codeword (450), and writing within a single clock cycle the interleaved data codeword to memory (460).

Abstract translation: 一种用于为存储在随机存取存储器（RAM）元件内的数据提供数据保护的方法（400）。 该方法包括接收要写入存储器的数据（420），将接收的数据划分成多个数据部分（430），向数据部分应用纠错码以形成码字部分（440），交织码字部分以形成 交织的数据码字（450），并且在单个时钟周期内将交织的数据码字写入存储器（460）。

公开(公告)号：WO2005010754A3

公开(公告)日：2005-04-14

申请号：PCT/US2004022353

申请日：2004-07-14

Applicant: INTEL CORP

Inventor： HOLMAN THOMAS

IPC: G06F11/00 ,  G06F11/10 ,  H03M13/00

CPC classification number: G11B20/1833 ,  G06F11/1028

Abstract: A circuit and method of generating an Error Correcting Code (ECC) based on an adjacent symbol codeword that is formed in two clock phases: generating a set of m bits, wherein m is an integer, of a first symbol and a set of m bits of a second symbol from a first set of data during a first clock phase; and generating a set of n bits, wherein n is an integer, of the first symbol and a set of n bits of the second symbol from a second set of data during a second clock phase.

Abstract translation: 一种基于以两个时钟相位形成的相邻符号码字来产生纠错码（ECC）的电路和方法：产生一组m位，其中m是第一符号和一组m位的整数 在第一时钟相位期间来自第一组数据的第二符号; 以及在第二时钟相位期间，从第二组数据生成第n个比特的n比特，其中n是第一符号的整数和第二符号的n比特的集合。

公开(公告)号：WO00073907A1

公开(公告)日：2000-12-07

申请号：PCT/US2000/014944

申请日：2000-05-30

IPC: G06F11/10 ,  G06F12/16 ,  G11B20/18 ,  H03M13/11 ,  H03M13/15 ,  H04L1/00 ,  G06F11/00

CPC classification number: G06F11/1028

Abstract: A system for protecting data and correcting bit errors due to component failures. A check bits generation unit partitions the data into a plurality of logical groups. The check bits generation unit generates a parity bit for each of the logical groups, and additionally generates a global error correction. The global error correction code is equivalent to the result of generating individual error correction codes for each logical group and combining them in a predetermined manner. In one particular embodiment, the data is divided into a total of X logical groups. An error correction unit is coupled to receive the plurality of data bits and the check bits following storage or transmission. It is configured to generate a parity error bit for each of the logical groups of data based on the received data bits, and to generate a regenerated global error correction code in the same manner in which the original global error correction code is derived. A global syndrome code is generated such that, with knowledge of the specific logical groups that have a single bit error, a value indicative of the location of the error in such groups may be derived from the global syndrome code.

Abstract translation: 用于保护数据并纠正由于组件故障导致的位错误的系统。 校验位生成单元将数据分割成多个逻辑组。 校验位生成单元为每个逻辑组生成奇偶校验位，并且还生成全局误差校正。 全局纠错码等效于为每个逻辑组产生各个纠错码并以预定的方式组合它们的结果。 在一个特定实施例中，数据被分成总共X个逻辑组。 耦合差错纠正单元以在存储或传输之后接收多个数据位和校验位。 它被配置为基于接收到的数据位产生每个逻辑数据组的奇偶校验错误位，并且以与原始全局误差校正码相同的方式产生再生全局纠错码。 生成全局校正码，使得通过具有单个位错误的特定逻辑组的知识，可以从全局校正子码导出指示这些组中的错误的位置的值。

公开(公告)号：WO1998009218A1

公开(公告)日：1998-03-05

申请号：PCT/DE1997001656

申请日：1997-08-06

Applicant: SIEMENS AKTIENGESELLSCHAFT ,  KNEFEL, Hans-Werner

Inventor： SIEMENS AKTIENGESELLSCHAFT

IPC: G06F11/10

CPC classification number: G06F11/1016 ,  G06F11/1028 ,  G06F11/2002 ,  G06F11/2017

Abstract: The data contained in storage systems are for the most part protected using an EDC system. If an error is present in the storage system, this error can be recognized by the EDC system only after the reading of incorrect data. The invention solves this problem.

Abstract translation: 存储系统的数据内容通常由EDC系统固定。 现在，如果错误存在于存储系统中，可以仅错误数据的读出后检测到该错误由EDC系统。 本发明解决了这个问题。

公开(公告)号：WO1997001138A1

公开(公告)日：1997-01-09

申请号：PCT/US1996009682

申请日：1996-06-10

Applicant: HAL COMPUTER SYSTEMS, INC.

Inventor： HAL COMPUTER SYSTEMS, INC. ,  SAXENA, Nirmal

IPC: G06F11/10

CPC classification number: G06F11/1028

Abstract: Methods and apparatuses allow a more compact error code which corrects and detects one or more bit errors and detects a memory chip failure to be used for the detection and correction of errors. Rather than store data in groups of bits equal to the width of the memory chip, data is stored in groups of bits smaller than the width of a chip. An error code is used which detects the failure of a chip having the width of the group. Because the group is smaller than the width of the chip, a smaller error code may be used.

Abstract translation: 方法和装置允许更紧凑的错误代码，其校正和检测一个或多个位错误并且检测存储器芯片故障被用于错误的检测和纠正。 不是将数据存储在等于存储器芯片的宽度的位组中，所以数据以小于芯片宽度的位组存储。 使用错误代码来检测具有该组宽度的芯片的故障。 由于该组小于芯片的宽度，所以可以使用较小的错误代码。

公开(公告)号：WO1987006737A1

公开(公告)日：1987-11-05

申请号：PCT/US1987000593

申请日：1987-03-17

Applicant: UNISYS CORPORATION

Inventor： UNISYS CORPORATION ,  KIM, Dongsung, Robert ,  KRONIES, Reinhard, Kurt

IPC: G06F11/10

CPC classification number: G06F11/1028

Abstract: A parity detection scheme for a wide memory structure of RAM memory chips (20) provides an auxiliary RAM parity memory chip (22) to store a parity data for each corresponding input line of each memory chip (20l...20q) corresponding for each address of each memory chip. This parity data is compared to comparable parity data which is read-out of any corresponding address of each of said memory chips.

公开(公告)号：WO1983002378A1

公开(公告)日：1983-07-07

申请号：PCT/US1982001759

申请日：1982-12-15

Applicant: SCIENTIFIC-ATLANTA, INC.

Inventor： SCIENTIFIC-ATLANTA, INC. ,  BANKER, Robert, O.

IPC: H04N07/16

CPC classification number: G06F11/1028 ,  H04N7/1713

Abstract: In order to provide higher efficiency of security in sync suppression scrambling of subscription TV signals, the signals are encoded with a timing pulse having a selected time delay relationship with the suppressed horizontal sync intervals of the TV signals. The timing can be implemented digitally by selecting a plurality (e.g., 12) of different timings. The timing can also be dynamically varied. The TV signals are descrambled by restoring the sync pulses at only those receiving stations authorized to receive the premium subscription programming which have circuits for generating restoring pulses with the selected time relationship upon reception of the timing signals. Accordingly, the use of unauthorized descramblers, which are insensitive to the timing signals or do not provide the restoring pulses in proper time relationship, is discouraged.