公开(公告)号：WO2011064754A1

公开(公告)日：2011-06-03

申请号：PCT/IB2010/055458

申请日：2010-11-26

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  ANTONAKOPOULOS, Theodore A. ,  CIDECIYAN, Roy D. ,  ELEFTHERIOU, Evangelos S. ,  HAAS, Robert ,  HU, Xiao-Yu ,  ILIADIS, Ilias

Inventor： ANTONAKOPOULOS, Theodore A. ,  CIDECIYAN, Roy D. ,  ELEFTHERIOU, Evangelos S. ,  HAAS, Robert ,  HU, Xiao-Yu ,  ILIADIS, Ilias

IPC: G06F11/10 ,  G11C29/00

CPC classification number: G06F11/1028 ,  G11C29/765

Abstract: Systems and methods are provided that confront the problem of failed storage integrated circuits (ICs) in a solid state drive (SSD) by using a fault-tolerant architecture along with one error correction code (ECC) mechanism for random/burst error corrections and an L-fold interleaving mechanism. The systems and methods described herein keep the SSD operational when one or more integrated circuits fail and allow the recovery of previously stored data from failed integrated circuits and allow random/burst errors to be corrected in other operational integrated circuits. These systems and methods replace the failed integrated circuits with fully functional/operational integrated circuits treated herein as spare integrated circuits. Furthermore, these systems and methods improve I/O performance in terms of maximum achievable read/write data rate.

Abstract translation: 提供了通过使用容错架构以及用于随机/突发错误校正的一个纠错码（ECC）机制来解决固态驱动器（SSD）中的故障存储集成电路（IC）的问题的系统和方法，以及 L折叠交织机制。 当一个或多个集成电路出现故障并且允许从故障集成电路恢复先前存储的数据并且允许在其他操作集成电路中校正随机/突发错误时，本文描述的系统和方法保持SSD的可操作性。 这些系统和方法用作为备用集成电路处理的全功能/可操作集成电路来代替故障集成电路。 此外，这些系统和方法在最大可实现的读/写数据速率方面提高了I / O性能。

公开(公告)号：WO2005010754A2

公开(公告)日：2005-02-03

申请号：PCT/US2004/022353

申请日：2004-07-14

Applicant: INTEL CORPORATION

Inventor： HOLMAN, Thomas

IPC: G06F11/00

CPC classification number: G11B20/1833 ,  G06F11/1028

Abstract: A circuit and method of generating an Error Correcting Code (ECC) based on an adjacent symbol codeword that is formed in two clock phases.

Abstract translation: 一种基于在两个时钟相位中形成的相邻符号码字来产生纠错码（ECC）的电路和方法。

公开(公告)号：WO0114971A9

公开(公告)日：2001-11-01

申请号：PCT/US0020960

申请日：2000-08-01

Applicant: SUN MICROSYSTEMS INC

Inventor： CYPHER ROBERT

IPC: G06F11/10 ,  H03M13/09 ,  H03M13/19

CPC classification number: G06F11/1024 ,  G06F11/1028

Abstract: A system for detecting and correcting errors in a data block includes a check bits generation unit which receives and encode data to be protected. The check bits generation unit partition the data into a plurality of logical groups. The check bits generation unit generates a parity bit for each of the logical group and additionally generates a pair of global error correction codes. The error correction unit is configured to generate a parity error bit for each of the logical group of data based on the received data and the original parity bits, as well as first and second syndrome codes.

Abstract translation: 用于检测和纠正数据块中的错误的系统包括校验比特生成单元，其接收和编码要保护的数据。 校验位生成单元将数据分割成多个逻辑组。 校验比特生成单元为每个逻辑组生成奇偶校验比特，并且另外生成一对全局误差校正码。 纠错单元被配置为基于接收到的数据和原始奇偶校验位以及第一和第二校正子代码为每个逻辑数据组产生奇偶校验错误位。

公开(公告)号：WO1998009216A1

公开(公告)日：1998-03-05

申请号：PCT/DE1997001644

申请日：1997-08-06

Applicant: SIEMENS AKTIENGESELLSCHAFT ,  KNEFEL, Hans-Werner

Inventor： SIEMENS AKTIENGESELLSCHAFT

IPC: G06F11/10

CPC classification number: G06F11/1016 ,  G06F11/1028 ,  G11B20/1833

Abstract: The data contained in a storage system are for the most part protected using EDC-processes. The storage system according to the invention is structured to make multi-bit errors more recognizable using the EDC process.

Abstract translation: 存储系统中的数据内容通常通过EDC方法固定。 根据本发明的存储系统被构造为使得多位错误的可见性在很大程度上受EDC方法改善。

公开(公告)号：WO2016082141A1

公开(公告)日：2016-06-02

申请号：PCT/CN2014/092342

申请日：2014-11-27

Applicant: 京微雅格(北京)科技有限公司

Inventor： 耿嘉 ,  王元鹏 ,  樊平

IPC: G11C7/10

CPC classification number: G06F11/1068 ,  G06F3/0604 ,  G06F3/0619 ,  G06F3/0629 ,  G06F3/064 ,  G06F3/0679 ,  G06F5/10 ,  G06F11/1028 ,  G06F11/1048 ,  G11C7/10 ,  G11C7/1075 ,  G11C29/52 ,  G11C2029/0411 ,  H03M13/05 ,  H03M13/19 ,  H03M13/2906

Abstract: 一种块存储器配置结构和配置方法,所述块存储器配置结构包括：第一端口，第二端口，ECC模块，FIFO模块；第一端口的读宽度和写宽度为不同值；第二端口的读宽度和写宽度为不同值；第一端口的读宽度和第二端口的读宽度为不同值，第一端口的写宽度和第二端口的写宽度为不同值；ECC模块，包括ECC编码器和ECC解码器；FIFO模块，用于对第一时钟使能端和第二时钟使能端进行设置，使得块存储器的读时钟和写时钟同步或读时钟和写时钟异步。该块存储器配置结构和配置方法，使得块存储器的读宽度和写宽度可以独立配置，块存储器内置ECC功能和FIFO功能，且不需要消耗额外的逻辑资源即可级联为存储空间更大的块存储器。

公开(公告)号：WO2011043791A2

公开(公告)日：2011-04-14

申请号：PCT/US2010/002556

申请日：2010-09-20

Applicant: MICRON TECHNOLOGY, INC. ,  JEDDELOH, Joseph, M.

Inventor： JEDDELOH, Joseph, M.

IPC: G06F13/10 ,  G06F12/00

CPC classification number: G06F11/08 ,  G06F3/0616 ,  G06F3/064 ,  G06F3/0688 ,  G06F11/1028 ,  G06F11/108

Abstract: The present disclosure includes methods and devices for stripe-based memory operation. One method embodiment includes writing data in a first stripe across a storage volume of a plurality of memory devices. A portion of the first stripe is updated by writing updated data in a portion of a second stripe across the storage volume of the plurality of memory devices. The portion of the first stripe is invalidated. The invalid portion of the first stripe and a remainder of the first stripe are maintained until the first stripe is reclaimed. Other methods and devices are also disclosed.

Abstract translation: 本公开包括用于基于条带的存储器操作的方法和设备。 一个方法实施例包括跨越多个存储器设备的存储卷在第一条带中写入数据。 第一条带的一部分通过在跨多个存储器装置的存储卷的第二条带的一部分中写入更新的数据而被更新。 第一个条纹的部分无效。 保持第一条带的无效部分和第一条带的其余部分，直到第一条带被回收。 其他方法和设备也被披露。

公开(公告)号：WO00017753A1

公开(公告)日：2000-03-30

申请号：PCT/US1999/022024

申请日：1999-09-22

IPC: G06F11/10 ,  G06F12/16 ,  G11C29/42 ,  H03M13/05

CPC classification number: G06F11/1028

Abstract: The bits of a data block are logically partitioned into an array that includes a number of columns equal to a number of memory devices and a number of rows equal to a number of bits of the data block stored in each memory device. Each memory device contributes one bit to each row. In one embodiment, the bits from a memory device are stored in the same column position of all the rows. One check bit is associated with each row. The check bit is computed by taking the parity of the row associated with the check bit and zero or one column. Each column is assigned to at least four check bits. If a check bit has a column assigned to it, then the check bit is generated by computing the parity of the associated row and the column assigned to the check bit. Alternatively, if the check bit does not have a column assigned to it, the check bit is generated by computing the parity of the row assigned to the check bit only. Each column is assigned to at least four check bits and is assigned to an even number of check bits.

Abstract translation: 数据块的位被逻辑地分割成包括等于多个存储器件的列数和等于存储在每个存储器件中的数据块的位数的数量的数组。 每个存储器件对每行贡献一位。 在一个实施例中，来自存储器设备的位被存储在所有行的相同列位置。 一个检查位与每一行相关联。 通过获取与校验位相关联的行的奇偶校验和零或一列来计算校验位。 每列分配至少四个检查位。 如果检查位具有分配给它的列，则通过计算相关联的行和分配给校验位的列的奇偶校验来生成校验位。 或者，如果检查位没有分配列，则通过计算仅分配给检查位的行的奇偶校验来生成校验位。 每列分配给至少四个校验位，并分配给偶数个校验位。

公开(公告)号：WO1998029811A1

公开(公告)日：1998-07-09

申请号：PCT/US1997021904

申请日：1997-11-24

Applicant: INTEL CORPORATION

Inventor： INTEL CORPORATION ,  HAYEK, George, R. ,  VENKATARAMAN, Radhakrishnan ,  AJANOVIC, Jasmin

IPC: G06F11/08

CPC classification number: G06F11/106 ,  G06F11/1028 ,  G06F11/1052 ,  G11C29/52 ,  G11C2029/0409

Abstract: Error correction circuitry (101) attempts to detect and correct, on-the-fly, erroneous words from RAM (102) within a computer system. Correctable errors are scrubbed without delaying the memory access cycle. The address of the section or row of RAM containing the correctable error is latched (130) for later use by a firmware-implemented interrupt-driven scrub routine (104) that reads and rewrites each word within the indicated memory section, resulting in the erroneous word being corrected on-the-fly and rewritten correctly. If the memory section size exceeds a threshold, the scrub process is divided into smaller subprocesses that are distributed in time using a delayed interrupt mechanism. Subprocess duration is kept short enough to avoid impairing the computer system response time. System management interrupts (120) and firmware (104) make the scrub routine independent of and transparent to the operating systems that may be run on the computer system.

Abstract translation: 错误校正电路（101）尝试从计算机系统内的RAM（102）中检测并纠正错误的单词。 擦除可纠正的错误，而不会延迟内存访问周期。 锁存包含可纠正错误的RAM的部分或一行的地址（130），供以后使用的固件实现的中断驱动擦除程序（104）读取并重写所指示的存储器部分中的每个字，导致错误 字被正确地修正并被正确地重写。 如果存储器部分大小超过阈值，则擦除处理被划分为使用延迟中断机制在时间上分布的更小的子处理。 子过程持续时间保持足够短以避免损害计算机系统响应时间。 系统管理中断（120）和固件（104）使擦洗程序独立于可能在计算机系统上运行的操作系统并且是透明的。

公开(公告)号：WO1983002345A1

公开(公告)日：1983-07-07

申请号：PCT/US1981001767

申请日：1981-12-30

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  CHEN, Chin-Long

Inventor： INTERNATIONAL BUSINESS MACHINES CORPORATION

IPC: G06F11/10

CPC classification number: G06F11/1028

Abstract: A modularized error correction apparatus for correcting package errors is provided by expanding an N bit single error correction, double error detection code to cover N packages of M bits each, so that the Exclusive-OR of all M bit single bit error syndromes in any given package results in a composite syndrome which is unique for each package. See Fig. 2 for the parity matrix H and the matching matrix M for the error correction code.

Abstract translation: 通过扩展N位单一错误校正，双重错误检测码来覆盖每个M位的N个包，提供用于校正包错误的模块化纠错装置，使得在任何给定的所有M位单位错误综合征中的异或 包装导致复合综合征，每种包装都是独一无二的。 见图。 2用于奇偶校验矩阵H和用于纠错码的匹配矩阵M.

公开(公告)号：WO2012048076A1

公开(公告)日：2012-04-12

申请号：PCT/US2011/055038

申请日：2011-10-06

Applicant: CLEVERSAFE, INC. ,  GLADWIN, S., Christopher

Inventor： GLADWIN, S., Christopher

IPC: H04K1/00

CPC classification number: H03M13/29 ,  G06F11/1028 ,  G06F11/1076 ,  G06F17/30194 ,  H03M13/05 ,  H03M13/1515 ,  H03M13/373 ,  H03M13/3761 ,  H04L45/24

Abstract: A method begins by a first device obtaining data for transmission to a second device and partitioning the data to produce a plurality of data portions. The method continues with the first device dispersed storage error encoding the plurality of data portions using a plurality of sets of error coding dispersal storage function parameters to produce a plurality of sets of encoded data slices and transmitting the plurality of sets of encoded data slices to the second device via a network. The method continues with a second device receiving at least a decode threshold number of encoded data slices and dispersed storage error decoding the at least a decode threshold number of encoded data slices to produce a decoded data portion for each set of the plurality of sets of encoded data slices. The method continues with the second device recapturing the data from a plurality of decoded data portions.

Abstract translation: 方法开始于第一设备获取用于传输到第二设备的数据并且划分数据以产生多个数据部分。 该方法继续使用多组错误编码分散存储功能参数来编码多个数据部分的第一设备分散存储错误，以产生多组编码数据片，并将多组编码数据片段发送到 第二设备通过网络。 该方法继续第二设备接收至少解码阈值数量的编码数据片和分散存储错误解码至少解码阈值数量的编码数据片以产生用于编码的多组编码数据片段中的每组的解码数据部分 数据片。 该方法继续，第二设备从多个解码的数据部分重新获取数据。