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    METHODS AND DEVICES FOR DECODING AND ENCODING DATA
    21.
    发明申请
    METHODS AND DEVICES FOR DECODING AND ENCODING DATA 审中-公开
    用于解码和编码数据的方法和设备

    公开(公告)号：WO2007053126A1

    公开(公告)日：2007-05-10

    申请号：PCT/SG2006/000337

    申请日：2006-11-07

    Applicant: AGENCY FOR SCIENCE, TECHNOLOGY AND RESEARCH ,  XU, Changlong ,  LIANG, Ying Chang ,  LEON, Wing Seng

    Inventor： XU, Changlong ,  LIANG, Ying Chang ,  LEON, Wing Seng

    IPC: H03M13/05

    CPC classification number: H03M13/616 ,  H03M13/19 ,  H03M13/2963 ,  H03M13/453

    Abstract: A method for decoding an input data sequence is provided. The method comprises generating a plurality of test sequences, determining an order for the plurality of test sequences, such that each test sequence differs from its adjacent test sequences by a respective predefined number of bits, and carrying out a maximum likelihood process with the ordered test sequences and the input data sequence thereby generating a maximum likelihood sequence.

    Abstract translation: 提供了一种用于解码输入数据序列的方法。 该方法包括生成多个测试序列，确定多个测试序列的顺序，使得每个测试序列与其相邻的测试序列不同于相应的预定位数，并且通过有序测试进行最大似然处理 序列和输入数据序列，从而产生最大似然序列。

    LDPC ENCODER AND DECODER AND LDPC ENCODING AND DECODING METHODS
    22.
    发明申请
    LDPC ENCODER AND DECODER AND LDPC ENCODING AND DECODING METHODS 审中-公开
    LDPC编码器和解码器和LDPC编码和解码方法

    公开(公告)号：WO2006062351A1

    公开(公告)日：2006-06-15

    申请号：PCT/KR2005/004177

    申请日：2005-12-07

    Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE ,  LEE, Sang Hyun ,  AHN, Jae Young

    Inventor： LEE, Sang Hyun ,  AHN, Jae Young

    IPC: H03M13/11

    CPC classification number: H03M13/1168 ,  H03M13/116 ,  H03M13/118 ,  H03M13/616 ,  H03M13/6356 ,  H03M13/6516

    Abstract: Provided are an LDPC encoder and decoder, and LDPC encoding and decoding methods. The LDPC encoder includes: a code generating circuit that includes a memory storing a first parity check matrix and sums a first row which is at least one row of the first parity check matrix and a second row which is at least one of the remaining rows of the first parity check matrix to output a second parity check matrix; and an encoding circuit receiving the second parity check matrix and an information word to output an LDPC-encoded code word. Also the LDPC decoder includes: a code generating circuit including a memory which stores a first parity check matrix and summing a first row which is at least one row of the first parity check matrix and a second row which is at least one of the remaining rows of the first parity check matrix to output a second parity check matrix; and a decoding circuit receiving the second parity check matrix and a code word to output an LDPC-decoded information word.

    Abstract translation: 提供了一种LDPC编码器和解码器，以及LDPC编码和解码方法。 LDPC编码器包括：代码生成电路，其包括存储第一奇偶校验矩阵的存储器，并且对作为第一奇偶校验矩阵的至少一行的第一行和与作为第一奇偶校验矩阵的剩余行中的至少一行的第二行求和 所述第一奇偶校验矩阵输出第二奇偶校验矩阵; 以及接收第二奇偶校验矩阵的编码电路和输出LDPC编码码字的信息字。 此外，LDPC解码器包括：代码生成电路，包括存储器，存储第一奇偶校验矩阵并对作为第一奇偶校验矩阵的至少一行的第一行求和作为剩余行中的至少一个的第二行 的第一奇偶校验矩阵以输出第二奇偶校验矩阵; 以及接收第二奇偶校验矩阵的解码电路和输出LDPC解码信息字的码字。

    A LOW DENSITY PARITY CHECK (LDPC) DECODER
    23.
    发明申请
    A LOW DENSITY PARITY CHECK (LDPC) DECODER 审中-公开
    低密度奇偶校验（LDPC）解码器

    公开(公告)号：WO2006055086A1

    公开(公告)日：2006-05-26

    申请号：PCT/US2005/033342

    申请日：2005-09-19

    Applicant: THOMSON LICENSING ,  GAO, Wen ,  RAMASWAMY, Kumar ,  STEWART, John, Sidney

    Inventor： GAO, Wen ,  RAMASWAMY, Kumar ,  STEWART, John, Sidney

    IPC: H03M13/11 ,  H03M13/00

    CPC classification number: H03M13/616 ,  H03M13/1105 ,  H03M13/1111 ,  H03M13/1137 ,  H03M13/1165 ,  H03M13/1168 ,  H03M13/1185

    Abstract: A satellite receiver comprises a front-end, demodulator and an LDPC decoder. The front-end receives a DVB-S2 LDPC coded signal and provides a down-converted signal to the demodulator. The latter demodulates the down-converted signal and provides a demodulated signal to the LDPC decoder. The LDPC decoder has a partially parallel architecture and partitions the bit node messages into N/360 groups and the check node messages into q groups, where q = M/360 . Each group is processed by 360 bit node processors or 360 check node processors, respectively. Illustratively, the LDPC decoder includes a memory that is partitioned such that messages associated with bit node groups are consecutively addressed. Alternatively, the LDPC decoder includes a memory that is partitioned such that messages associated with check node groups are consecutively addressed.

    Abstract translation: 卫星接收机包括前端，解调器和LDPC解码器。 前端接收DVB-S2 LDPC编码信号，并向解调器提供下变频信号。 后者解调下变频信号并向LDPC解码器提供解调信号。 LDPC解码器具有部分并行架构，并将比特节点消息划分为N / 360组，并将校验节点消息分为q组，其中q = M / 360。 每个组分别由360位节点处理器或360个校验节点处理器处理。 说明性地，LDPC解码器包括分区的存储器，使得与位节点组相关联的消息被连续寻址。 或者，LDPC解码器包括被分区的存储器，使得与校验节点组相关联的消息被连续寻址。

    ＬＤＰＣ符号生成方法、通信装置および符号列生成方法
    24.
    发明申请
    ＬＤＰＣ符号生成方法、通信装置および符号列生成方法 审中-公开
    LDPC代码创建方法，通信设备和代码序列创建方法

    公开(公告)号：WO2006027897A1

    公开(公告)日：2006-03-16

    申请号：PCT/JP2005/012949

    申请日：2005-07-13

    Applicant: 三菱電機株式会社 ,  内田 繁 ,  大塚 晃 ,  松本 渉

    Inventor： 内田 繁 ,  大塚 晃 ,  松本 渉

    IPC: H03M13/19

    CPC classification number: H03M13/118 ,  H03M13/033 ,  H03M13/1185 ,  H03M13/255 ,  H03M13/353 ,  H03M13/356 ,  H03M13/616

    Abstract: 　本発明にかかるＬＤＰＣ符号生成方法は、多値変調方式に適用可能なＬＤＰＣ符号生成方法であって、たとえば、変調シンボルのビット位置毎に受信信号の分布を分類した上で、ＳＮＲしきい値（符号長が十分に長い場合にビット誤り率が急峻に落ちるＳＮＲの値）が最小となるようなパリティ検査行列の次数アンサンブル（行の重みと列の重みのアンサンブル）を探索し、さらに、前記探索結果として得られた次数アンサンブルに基づいて、パリティ検査行列、生成行列を生成することとした。

    Abstract translation: 适用于多值调制的LDPC码创建方法。 例如，在对调制符号的每个比特位置分配接收信号的分配之后，将奇偶校验矩阵的秩集合（线和列的权重的集合）最小化以使SNR阈值（SNR值在 寻求代码长度足够大时误码率急剧下降的奇偶校验矩阵和创建矩阵，作为搜索结果获取的顺序集合。

    METHOD AND APPARATUS FOR DECODING TURBO-ENCODED CODE SEQUENCE
    25.
    发明申请
    METHOD AND APPARATUS FOR DECODING TURBO-ENCODED CODE SEQUENCE 审中-公开
    用于解码涡轮编码序列的方法和装置

    公开(公告)号：WO01082490A1

    公开(公告)日：2001-11-01

    申请号：PCT/JP2001/002355

    申请日：2001-03-23

    IPC: H03M13/29 ,  H03M13/45

    CPC classification number: H03M13/3905 ,  H03M13/2957 ,  H03M13/3933 ,  H03M13/616

    Abstract: A decoding method is started with initialization of a forward regression probability function vector alpha 0 and a backward regression probability function vector beta N. Transition probability matrixes GAMMA (Rk) and GAMMA i(Rk) are then determined depending on each received code of a sequence R1 . Subsequently, the value of a vector alpha k corresponding to the received Rk is determined depending on the GAMMA (Rk). A plurality of multiplications related to the GAMMA (Rk) and GAMMA i(Rk) are performed in parallel with determination of the alpha k. After receiving a complete code sequence R1 , all values of a backward regression probability function vector beta k (k=1, 2, ..., N-1) are determined in parallel utilizing the results of matrix multiplication and a logarithmic likelihood ratio related to each decoded bit dk (k=1, 2, ..., N) is determined in parallel. The circuit performs continuous decoding in parallel using a series of regular matrix operations.

    Abstract translation: 通过初始化前向回归概率函数向量α0和反向回归概率函数向量βN开始解码方法。然后根据序列的每个接收到的代码来确定转移概率矩阵GAMMA（Rk）和GAMMA i（Rk） R1 。 随后，根据GAMMA（Rk）确定与接收的Rk对应的向量αk的值。 与确定αk并行执行与GAMMA（Rk）和GAMMA i（Rk）相关的多个乘法。 在收到完整的代码序列R1 后，使用矩阵乘法的结果并行地确定反向回归概率函数向量βk（k = 1,2，...，N-1）的所有值 与每个解码位dk（k = 1,2，...，N）相关的似然比被并行确定。 该电路使用一系列常规矩阵运算并行执行连续解码。

    LOOK-AHEAD LDPC DECODER
    26.
    发明申请
    LOOK-AHEAD LDPC DECODER 审中-公开

    公开(公告)号：WO2019040638A1

    公开(公告)日：2019-02-28

    申请号：PCT/US2018/047553

    申请日：2018-08-22

    Applicant: GOKE US RESEARCH LABORATORY

    Inventor： TSENG, Ko-Chung ,  YEO, Engling

    IPC: H03M13/11 ,  H03M13/47

    CPC classification number: H03M13/1131 ,  H03M13/1111 ,  H03M13/116 ,  H03M13/616 ,  H03M13/6525

    Abstract: Look-ahead LDPC decoder. In an exemplary embodiment, a method includes generating a message (QA) to a first check node, the QA message is generated from a result (RA) from the first check node, and generating a message (QB) to a second check node, the QB message is generated from the result (RA) and is transmitted to avoid decoder stall. The method also includes receiving a result (R'A) from the first check node, computing a difference (R''A) between the result (R'A) and the result (RA), and receiving a result (R'B) from the second check node. The method also includes computing a bit value P(B) using the difference (R''A) and the result (R'B).

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