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    TRANSFORM UNIT DESIGN FOR VIDEO CODING
    35.
    发明申请
    TRANSFORM UNIT DESIGN FOR VIDEO CODING 审中-公开

    公开(公告)号：WO2021055746A1

    公开(公告)日：2021-03-25

    申请号：PCT/US2020/051490

    申请日：2020-09-18

    Applicant: QUALCOMM INCORPORATED

    Inventor： RAMASUBRAMONIAN, Adarsh Krishnan ,  VAN DER AUWERA, Geert ,  SEREGIN, Vadim ,  KARCZEWICZ, Marta

    IPC: H04N19/119 ,  H04N19/176 ,  H04N19/186 ,  H04N19/70

    Abstract: An example device includes a memory and one or more processors. The one or more processors are configured to determine whether a first coding tree unit (CTU) is coded using single tree and based on the first CTU being coded using single tree, determine a first transform unit (TU) based on a first transform block (TB) of luma samples and a first two corresponding TBs of chroma samples. The one or more processors are also configured to determine whether a second CTU is coded using dual tree and based on the second CTU being coded using dual tree, determine a second TU based on either (i) a second TB of luma samples or (ii) a second two TBs of chroma samples. The first TU includes syntax structures used to transform first TB samples and the second TU includes syntax structures used to transform second TB samples.

    PALETTE AND PREDICTION MODE SIGNALING
    36.
    发明申请
    PALETTE AND PREDICTION MODE SIGNALING 审中-公开

    公开(公告)号：WO2021026111A1

    公开(公告)日：2021-02-11

    申请号：PCT/US2020/044817

    申请日：2020-08-04

    Applicant: QUALCOMM INCORPORATED

    Inventor： CHAO, Yung-Hsuan ,  HUNG, Chao-Hsiung ,  CHIEN, Wei-Jung ,  KARCZEWICZ, Marta

    IPC: H04N19/176 ,  H04N19/593 ,  H04N19/70

    Abstract: An example device for decoding video data includes a memory for storing the video data and one or more processors implemented in circuitry and communicatively coupled to the memory. The one or more processors are configured to determine whether a first coding unit (CU) is a skip mode CU, and based on the first CU not being a skip mode CU, determine whether the first CU is encoded using one of an intra mode or a palette mode. The one or more processors are also configured to determine whether the first CU is encoded using the palette mode based on the first CU being encoded using one of the intra mode or the palette mode. The one or more processors are also configured to decode the first CU based on the determination of whether the first CU is encoded using the palette mode.

    CONTROLLING RENDERING OF AUDIO DATA
    39.
    发明申请
    CONTROLLING RENDERING OF AUDIO DATA 审中-公开

    公开(公告)号：WO2022072131A1

    公开(公告)日：2022-04-07

    申请号：PCT/US2021/049661

    申请日：2021-09-09

    Applicant: QUALCOMM INCORPORATED

    Inventor： MUNOZ, Isaac Garcia

    IPC: H04S7/00 ,  G06F3/16 ,  H04R5/033 ,  H04R3/00

    Abstract: Example devices, systems and methods for processing audio data are disclosed. An example device includes a memory configured to store one or more speaker feeds and one or more processors implemented in circuitry and communicatively coupled to the memory. The one or more processors are configured to determine whether a boundary separating an interior area from an exterior area exists, and based on the boundary existing, determine a transition distance value, the transition distance value being indicative of a size of a transition zone. The one or more processors are configured to obtain a listener location indicative of a virtual location of the device relative to the interior area and obtain, based at least in part on the boundary and the listener location, a current renderer. The one or more processors are configured to apply, to the audio data, the current renderer to obtain the one or more speaker feeds.

    DYNAMIC RANGE ADJUSTMENT PARAMETER SIGNALING AND ENABLEMENT OF VARIABLE BIT DEPTH SUPPORT
    40.
    发明申请
    DYNAMIC RANGE ADJUSTMENT PARAMETER SIGNALING AND ENABLEMENT OF VARIABLE BIT DEPTH SUPPORT 审中-公开

    公开(公告)号：WO2021207589A1

    公开(公告)日：2021-10-14

    申请号：PCT/US2021/026561

    申请日：2021-04-09

    Applicant: QUALCOMM INCORPORATED

    Inventor： RUSANOVSKYY, Dmytro ,  RAMASUBRAMONIAN, Adarsh Krishnan ,  ZHANG, Yan ,  KARCZEWICZ, Marta

    IPC: H04N19/186 ,  H04N19/169 ,  H04N19/70 ,  H04N19/85

    Abstract: An example device for processing video data includes memory configured to store the video data and one or more processors implemented in circuitry and coupled to the memory. The one or more processors are configured to parse a first parameter set, the first parameter set being signaled in a bitstream data once per sequence of a group of encoded pictures. The one or more processors are configured to parse one or more dynamic range adjustment (DRA) syntax elements in a second parameter set, the second parameter set being signaled in the bitstream and being related to at least one picture in the group of encoded pictures, wherein the parsing of the one or more DRA syntax elements is not dependent on any syntax element of the first parameter set, and process the at least one picture based on the first parameter set and the second parameter set.

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