公开(公告)号：WO2007036800A2

公开(公告)日：2007-04-05

申请号：PCT/IB2006002766

申请日：2006-09-28

Applicant: ATI TECHNOLOGIES INC ,  ATI INT SRL ,  ALEKSIC MILIVOJE ,  GOMA SERGIU

Inventor： ALEKSIC MILIVOJE ,  GOMA SERGIU

IPC: H03M13/00 ,  H04L1/00

CPC classification number: H04L1/0057 ,  H03M13/19 ,  H03M13/27 ,  H04L1/0083

Abstract: To derive a Hamming code to manage data errors a set of at least four parity bit positions is selected for parity bits which will protect a set of data bits (where each data bit has a data bit position in the data bit set). A syndrome is determined for each data bit position. This involves selecting a unique sub-set of at least three parity bit positions. The unique sub-set shares at least one parity bit position with at least one other unique sub-set of at least three parity bit positions. A parity bit value may then be calculated for each parity bit position based on the determined syndromes. The header of a packet may be provided with a word which defines the length of the packet and an error management code generated utilizing this word so that errors in the word may be detected and, possibly, corrected.

Abstract translation: 为了导出汉明码以管理数据错误，为奇偶校验位选择至少四个奇偶校验位位置的集合，这将保护一组数据位（其中每个数据位在数据位集合中具有数据位位置）。 针对每个数据位位置确定综合征。 这包括选择至少三个奇偶校验位位置的唯一子集。 唯一子集与至少三个奇偶校验位位置的至少一个其他唯一子集共享至少一个奇偶校验位位置。 然后可基于所确定的校验子为每个奇偶校验位位置计算奇偶校验位值。 分组的报头可以提供有定义分组长度的字和利用该字生成的错误管理码，以便可以检测并且可能校正该字中的错误。

公开(公告)号：WO2005085977A2

公开(公告)日：2005-09-15

申请号：PCT/IB2005000566

申请日：2005-03-02

Applicant: ATI TECHNOLOGIES INC ,  ATI INT SRL ,  KHODORKOVSKY OLEKSANDR

Inventor： KHODORKOVSKY OLEKSANDR

IPC: G06F1/04 ,  G06F1/32 ,  G09G5/18

CPC classification number: G09G5/18 ,  G06F1/3218 ,  G06F1/3225 ,  G06F1/324 ,  G06F1/3265 ,  G06F1/3275 ,  G09G2330/021 ,  Y02D10/126 ,  Y02D10/14 ,  Y02D10/153

Abstract: A variable clock control information generator receives graphics engine activity data relating to the operating level of a graphics engine, and memory activity data relating to an activity level of memory. In response, the variable clock control information generator produces graphics engine clock control information and memory clock control information with respect to each other, such that a relative difference between the graphics engine activity data and the memory activity data is within balance threshold data. Accordingly, the variable clock control information generator adapts to the varying levels of graphics engine activity and memory activity and adjusts the frequency of the graphics engine clock signal and the frequency of the memory clock signal to achieve a balanced relative activity level.

Abstract translation: 可变时钟控制信息生成器接收与图形引擎的操作级别相关的图形引擎活动数据，以及与存储器的活动级别相关的存储器活动数据。 作为响应，可变时钟控制信息发生器相对于彼此产生图形引擎时钟控制信息和存储器时钟控制信息，使得图形引擎活动数据和存储器活动数据之间的相对差异在平衡阈值数据内。 因此，可变时钟控制信息发生器适应图形引擎活动和存储器活动的变化水平，并且调整图形引擎时钟信号的频率和存储器时钟信号的频率以实现平衡的相对活动水平。