公开(公告)号：WO2009016497A2

公开(公告)日：2009-02-05

申请号：PCT/IB2008002032

申请日：2008-08-01

Applicant: ADVANCED MICRO DEVICES INC ,  ATI INT SRL ,  CHAN VINCENT ,  MCLELLAN NEIL ,  O'NEIL KEVIN

Inventor： CHAN VINCENT ,  MCLELLAN NEIL ,  O'NEIL KEVIN

CPC classification number: H01L24/11 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/18 ,  H01L2224/05001 ,  H01L2224/05022 ,  H01L2224/05026 ,  H01L2224/05139 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05169 ,  H01L2224/05571 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05655 ,  H01L2224/05669 ,  H01L2224/1132 ,  H01L2224/11334 ,  H01L2224/1147 ,  H01L2224/13099 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13169 ,  H01L2224/16145 ,  H01L2224/73253 ,  H01L2225/06513 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/1532 ,  H01L2924/30107 ,  H01L2924/00014

Abstract: Various stacked semiconductor devices and methods of making the same are provided. In one aspect, a method of manufacturing is provided that includes providing a first semiconductor die that has a first bulk semiconductor side and a first opposite side. A second semiconductor die is provided that has a second bulk semiconductor side and a second opposite side. The second opposite side of the second semiconductor die is coupled to the first opposite side of the first semiconductor die. Electrical connections are formed between the first semiconductor die and the second semiconductor die.

Abstract translation: 提供了各种堆叠的半导体器件及其制造方法。 在一个方面，提供了一种制造方法，其包括提供具有第一体半导体侧和第一相对侧的第一半导体管芯。 提供第二半导体管芯，其具有第二体半导体侧和第二相对侧。 第二半导体管芯的第二相对侧耦合到第一半导体管芯的第一相对侧。 在第一半导体管芯和第二半导体管芯之间形成电连接。

公开(公告)号：WO2007117526A3

公开(公告)日：2008-04-17

申请号：PCT/US2007008438

申请日：2007-04-03

Applicant: ATI TECHNOLOGIES INC ,  ATI INT SRL ,  MACRI JOSEPH ,  GAUTHIER CLAUDE ,  LEE MING-JU E ,  MOREIN STEPHEN ,  CHEN LIN

Inventor： MACRI JOSEPH ,  GAUTHIER CLAUDE ,  LEE MING-JU E ,  MOREIN STEPHEN ,  CHEN LIN

IPC: G06F1/26 ,  G06F1/04

CPC classification number: G06F1/3203 ,  G06F1/3253 ,  Y02D10/151 ,  Y02D50/20

Abstract: Embodiments of a power consumption reduction process for memory interfaces are described. A power management process reduces the amount of time that current flows in a high or low terminated, current or voltage mode unipolar bus interface by reducing the amount of time the bus remains in a logic state that requires current flow.

Abstract translation: 描述用于存储器接口的功耗降低过程的实施例。 电源管理过程通过减少总线保持在需要电流的逻辑状态的时间量，减少电流在高或低端接，电流或电压模式单极总线接口中流动的时间。

公开(公告)号：WO2006126090A3

公开(公告)日：2007-08-23

申请号：PCT/IB2006001463

申请日：2006-05-26

Applicant: ATI TECHNOLOGIES INC ,  ATI INT SRL ,  KELLY TIM ,  CAMPBELL JON ,  GOTWALT DAVID

Inventor： KELLY TIM ,  CAMPBELL JON ,  GOTWALT DAVID

IPC: G06F9/38

CPC classification number: G06F9/30069 ,  G06F9/30072 ,  G06F9/3885

Abstract: A system and method for applying non-homogeneous properties to multiple video processing units (VPUs) in a multiple VPU system are described. Respective VPUs in the system cooperate to produce a frame to be displayed. In various embodiments, data output by different VPUs in the system is combined, or merged, or composited to produce a frame to be displayed. In load balancing modes, each VPU in the system performs different tasks as part of rendering a same frame, and therefore typically executes different commands. In various embodiments, efficiency of the system is enhanced by forming a single command buffer for execution by all of the VPUs in the system even though each VPU may have a different set of commands to execute in the command buffer.

Abstract translation: 描述了将多个VPU系统中的多个视频处理单元（VPU）应用非均匀特性的系统和方法。 系统中的相应VPU协同生成要显示的帧。 在各种实施例中，由系统中的不同VPU输出的数据被组合，合并或合成以产生要显示的帧。 在负载平衡模式下，系统中的每个VPU执行不同的任务作为渲染相同帧的一部分，因此通常执行不同的命令。 在各种实施例中，即使每个VPU可以具有在命令缓冲器中执行的不同命令集，通过形成用于系统中的所有VPU执行的单个命令缓冲器来增强系统的效率。

公开(公告)号：WO2007036801A3

公开(公告)日：2007-07-12

申请号：PCT/IB2006002780

申请日：2006-09-28

Applicant: ATI TECHNOLOGIES INC ,  ATI INT SRL ,  ALEKSIC MILIVOJE ,  GOMA SERGIU

Inventor： ALEKSIC MILIVOJE ,  GOMA SERGIU

IPC: G06F1/32

CPC classification number: G06F1/3203 ,  G06F1/3253 ,  G06F13/4282 ,  Y02D10/151

Abstract: A method of operating a shared bus comprises sending a wake-up signal on the shared bus. The wake-up signal comprises a sequence of signals, each signal of the sequence being one of a signal indicating the bus is free and a signal indicating the bus is busy. A microcontroller to effect this method is also contemplated. A wake-up device for a shared bus has a first latch to recognise a signal indicating one of said shared bus being free and said shared bus being busy and selectively output a recognition signal and a second latch to, after receipt of the recognition signal, recognise a signal indicating another of the shared bus being free and Ihe shared bus being busy and selectively output a power-on signal. The latches may be D -type flip flops.

Abstract translation: 一种操作共享总线的方法包括在共享总线上发送唤醒信号。 唤醒信号包括一系列信号，序列的每个信号是指示总线空闲的信号之一，并且指示总线忙的信号。 也考虑了实现该方法的微控制器。 用于共享总线的唤醒装置具有第一锁存器，用于识别指示所述共享总线中的一个是空闲的信号，并且所述共享总线正忙，并且在接收到识别信号之后选择性地输出识别信号和第二锁存器， 识别指示共享总线中的另一个是空闲的信号，并且共享总线正在忙，并选择性地输出开机信号。 锁存器可以是D型触发器。

公开(公告)号：WO2007026243A3

公开(公告)日：2007-07-12

申请号：PCT/IB2006002451

申请日：2006-08-31

Applicant: ATI TECHNOLOGIES INC ,  ATI INT SRL ,  ALEKSIE MILIVOJE

Inventor： ALEKSIE MILIVOJE

IPC: H04N7/26

CPC classification number: H04B7/12 ,  H04B7/0619 ,  H04B7/0828 ,  H04B7/0837 ,  H04B7/084 ,  H04N19/40

Abstract: A method and apparatus for communicating compressed video information includes storing video information compressed based on a first compression method, such as a method with a high compression ratio, and transcoding the compressed video information to produce corresponding recompressed video information that is based on a second compression method, with a lower compression ratio such as standard JPEG compression or other suitable compression. The method and apparatus, if desired, may include sending the recompressed video information for a destination apparatus which may then suitably decompress the video information using a standard decompression technique. For example, storing the compressed image in a high compressed format, for example, in a piecewise basis may be done online while the camera, for example, is in use so that the image is properly captured and then, transcoding the compressed image to a different level of compression while the camera is offline.

Abstract translation: 用于传送压缩视频信息的方法和装置包括：存储基于第一压缩方法压缩的视频信息，例如具有高压缩率的方法，以及对压缩视频信息进行代码转换以产生基于第二压缩的对应的再压缩视频信息 方法，具有较低的压缩比例如标准JPEG压缩或其他合适的压缩。 如果需要，该方法和装置可以包括发送用于目的地装置的经重新压缩的视频信息，该目的地装置然后可以使用标准解压缩技术适当地解压缩视频信息。 例如，例如以分段方式以高压缩格式存储压缩图像可以在例如相机被在线使用的情况下在线完成，从而适当地捕获图像，然后将压缩图像代码转换为 相机处于脱机状态时的不同级别的压缩。

公开(公告)号：WO0045257A3

公开(公告)日：2001-03-08

申请号：PCT/US0002239

申请日：2000-01-28

Applicant: ATI INT SRL ,  YATES JOHN S JR ,  REESE DAVID L ,  HOHENSEE PAUL H ,  ADLER MICHAEL C ,  DYKE KORBIN S VAN ,  RAMESH T R ,  THUSOO SHALESH ,  SAUND GURJEET SINGH ,  PURCELL STEPHEN C ,  PATKAR NITEEN ARAVIND ,  NIJHAWAN SANDEEP ,  STORCH MATTHEW F ,  JURICH DALE R ,  CAMPBELL PAUL

Inventor： YATES JOHN S JR ,  REESE DAVID L ,  HOHENSEE PAUL H ,  ADLER MICHAEL C ,  VAN DYKE KORBIN S ,  RAMESH T R ,  THUSOO SHALESH ,  SAUND GURJEET SINGH ,  PURCELL STEPHEN C ,  PATKAR NITEEN ARAVIND ,  NIJHAWAN SANDEEP ,  STORCH MATTHEW F ,  JURICH DALE R ,  CAMPBELL PAUL

IPC: G06F12/08 ,  G06F9/30 ,  G06F9/455 ,  G06F9/46 ,  G06F12/10 ,  G06F9/318 ,  G06F9/38

CPC classification number: G06F9/30189 ,  G06F9/30174 ,  G06F9/3808 ,  G06F9/455

Abstract: A computer able to execute programs coded in either of two binary instruction sets. Memory is divided into regions, and each region is marked to indicate which of the two instruction sets are to be used to execute instructions fetched from that region. The native operating system manages contexts so that the operating system for the guest instruction set architecture can context switch, even if the process being context-switched out is a process in the native instruction set. Code in the guest instruction set is profiled to determine which portions are most profitably translated into the native instruction set. Circuitry recognizes when execution of a binary in the guest instruction set has reached a flow point for which a translated native equivalent exists. Concurrency controls protect the translated native code against modification by self-modifying code or DMA writes.

Abstract translation: 能够执行以两个二进制指令集中的任何一个编码的程序的计算机。 存储器被分成区域，并且每个区域被标记以指示两个指令集中的哪一个用于执行从该区域获取的指令。 本地操作系统管理上下文，使得用于客户指令集体系结构的操作系统可以上下文切换，即使上下文切换的进程是本机指令集中的进程。 访客指令集中的代码被分析，以确定哪些部分最有利地转换为本机指令集。 电路识别在客户指令集中的二进制数据的执行已经达到翻译的本机等价物的流程点时。 并发控制通过自修改代码或DMA写入保护翻译的本机代码免受修改。

公开(公告)号：WO2009071982A2

公开(公告)日：2009-06-11

申请号：PCT/IB2008003343

申请日：2008-12-04

Applicant: ATI TECHNOLOGIES ULC ,  ATI INT SRL ,  MCLELLAN NEIL ,  LI YUE ,  TOPACIO RODEN ,  CHEUNG TERENCE

Inventor： MCLELLAN NEIL ,  LI YUE ,  TOPACIO RODEN ,  CHEUNG TERENCE

IPC: H01L23/485 ,  H01L21/60 ,  H01L23/525

CPC classification number: H01L24/13 ,  H01L21/563 ,  H01L23/50 ,  H01L23/525 ,  H01L23/5286 ,  H01L24/11 ,  H01L2224/10126 ,  H01L2224/1132 ,  H01L2224/1147 ,  H01L2224/1148 ,  H01L2224/13007 ,  H01L2224/13022 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2224/1411 ,  H01L2224/16 ,  H01L2224/73203 ,  H01L2924/0001 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01059 ,  H01L2924/01075 ,  H01L2924/01076 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12044 ,  H01L2924/1306 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/19041 ,  H01L2924/30107 ,  H01L2924/351 ,  H01L2924/00

Abstract: Various semiconductor chip conductor structures and methods of fabricating the same are provided. In one aspect, a method of manufacturing is provided that includes forming a conductor structure on a semiconductor chip. The conductor structure has a first site electrically connected to a first redistribution layer structure and a second site electrically connected to a second redistribution layer structure. A solder structure is formed on the conductor structure.

Abstract translation: 提供各种半导体芯片导体结构及其制造方法。 一方面，提供一种制造方法，其包括在半导体芯片上形成导体结构。 导体结构具有电连接到第一再分配层结构的第一部位和电连接到第二再分配层结构的第二部位。 在导体结构上形成焊料结构。

公开(公告)号：WO2007072211A3

公开(公告)日：2007-10-04

申请号：PCT/IB2006003814

申请日：2006-12-21

Applicant: ATI TECHNOLOGIES INC ,  ATI INT SRL ,  STRASSER DAVID A

Inventor： STRASSER DAVID A

IPC: H04N5/00 ,  H04N7/16 ,  H04N7/24

CPC classification number: H04N21/4623 ,  H04N21/4143 ,  H04N21/418 ,  H04N21/4181 ,  H04N21/4183 ,  H04N21/4305 ,  H04N21/440218 ,  H04N21/4405 ,  H04N21/4621

Abstract: To receive new services including audio or video content for presentation by a cable-compatible digital television or other digital audio/video receiver, a module may be connected to the HOST-POD interface of the digital television. The module has a receiver for receiving audio or video content in a first compression format, a transcoder for converting said audio or video content from the first compression format into a second, different compression format, and a controller for transmitting the audio or visual content in the second compression format to the digital television over a HOST-POD interface. By using such a module, front-end components of the digital television may be bypassed while back-end components may be utilized to decompress and present the content. The module may be a PC card or smart card for example.

Abstract translation: 为了接收新的服务，包括音频或视频内容，用于由电缆兼容的数字电视或其他数字音频/视频接收机呈现，模块可以连接到数字电视的HOST-POD接口。 该模块具有用于以第一压缩格式接收音频或视频内容的接收器，用于将所述音频或视频内容从第一压缩格式转换成第二不同压缩格式的代码转换器，以及用于将音频或视频内容传输到 通过HOST-POD接口向数字电视提供第二种压缩格式。 通过使用这样的模块，数字电视的前端组件可以被旁路，而后端组件可以用于解压缩并呈现内容。 该模块可以是例如PC卡或智能卡。

公开(公告)号：WO2007085963A2

公开(公告)日：2007-08-02

申请号：PCT/IB2007000260

申请日：2007-01-30

Applicant: ATI TECHNOLOGIES INC ,  ATI INT SRL ,  SAGALOVITCH SERGUEI ,  CHAN HING PONG ,  YURIN ALEXEI

Inventor： SAGALOVITCH SERGUEI ,  CHAN HING PONG ,  YURIN ALEXEI

CPC classification number: G06F9/4881 ,  G06F9/485

Abstract: To provide for the processing of priority data elements between a host processor and a co- processor that exchange such data elements using a queue, the host processor determines a priority of a data element received from an application. If the priority is higher than a lowest possible priority value, at least one lower priority data element within the queue may be identified and modified thereby temporarily removing it from the queue. When the priority data element is written into the queue a query packet is included that will cause the co-processor to return information regarding a last executed queued data element. Based on the returned information, the host processor can determine one or more unmodified data elements (uniquely corresponding to the one or more modified queued data elements) to be written into the queue in accordance with a sequence of the previously modified queued data elements.

Abstract translation: 为了提供在主机处理器和使用队列交换这样的数据元素的协处理器之间的优先级数据元素的处理，主处理器确定从应用接收的数据元素的优先级。 如果优先级高于最低可能的优先级值，则可以识别和修改队列内的至少一个较低优先级的数据元素，从而将其临时从队列中移除。 当优先级数据元素被写入队列时，包括查询分组，这将使协处理器返回关于最后执行的排队数据元素的信息。 基于返回的信息，主机处理器可以根据先前修改的排队数据元素的顺序来确定要写入队列的一个或多个未修改数据元素（唯一对应于一个或多个修改后的排队数据元素）。

公开(公告)号：WO2006129194A3

公开(公告)日：2007-02-22

申请号：PCT/IB2006001702

申请日：2006-05-26

Applicant: ATI TECHNOLOGIES INC ,  ATI INT SRL ,  KELLY TIM ,  KADURI RAJA ,  BEHR DOMINIK

Inventor： KELLY TIM ,  KADURI RAJA ,  BEHR DOMINIK

IPC: G06T15/00

CPC classification number: G06T15/005 ,  G06F9/52 ,  G06T1/20 ,  G06T2210/52

Abstract: A system and method for frame synchronization in multiple video processing unit (VPU) systems is described. In various embodiments, multiple VPUs cooperatively process frame data for display. According to embodiments, more than one VPU may not reside on a same card such that conventional synchronization methods are available. Frame data synchronization is accomplished in various embodiments by using semaphore mechanisms and by writing values to shared memory locations. For synchronization of execution among multiple VPUs operating on a same command buffer, execution of commands by one or more VPUs is stalled based on a semaphore value or a value in a shared memory location.

Abstract translation: 描述了用于多视频处理单元（VPU）系统中的帧同步的系统和方法。 在各种实施例中，多个VPU协同处理帧数据以进行显示。 根据实施例，多于一个VPU可能不驻留在同一卡上，使得传统的同步方法是可用的。 帧数据同步在各种实施例中通过使用信号量机制和将值写入共享存储器位置来实现。 为了在同一命令缓冲器上操作的多个VPU之间的执行同步，一个或多个VPU的命令的执行基于信号量值或共享存储器位置中的值而停止。