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公开(公告)号:WO2020069203A1
公开(公告)日:2020-04-02
申请号:PCT/US2019/053275
申请日:2019-09-26
Applicant: INTEL CORPORATION
Inventor: BOOS, Zdravko
Abstract: A clock generator can include a Fin Field Effect Transistor (FinFET) oscillator and a phased-locked loop (PLL). The FinFET oscillator can generate a FinFET signal. The PLL can generate an output clock signal based on a reference clock signal and the FinFET signal.
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公开(公告)号:WO2020056836A1
公开(公告)日:2020-03-26
申请号:PCT/CN2018/111232
申请日:2018-10-22
Applicant: 天津大学
IPC: H03B5/30
Abstract: 一种柔性射频振荡器,其解决了现有技术中存在的柔韧性差、应用范围狭窄的技术问题。该柔性射频振荡器包括:柔性基底(11)、选频网络(12)、柔性电学元件(13)以及柔性电路连接(14),其中:选频网络(12)、柔性电学元件(13)以及柔性电路连接(14)均位于柔性基底(11)之上;选频网络(12)用于获得所需频率范围的信号;柔性电路连接(14)用于将选频网络(12)和柔性电学元件(13)进行电学连接。
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公开(公告)号:WO2020036669A3
公开(公告)日:2020-02-20
申请号:PCT/US2019/036628
申请日:2019-06-11
Inventor: NAGULU, Aravind , KRISHNASWAMY, Harish
Abstract: A circulator, comprising: a gyrator having a first side (1S) and a second side (2S) connected to a third port; a first transmission line section (TLS) having a 1 S connected to the 1 S of the gyrator and a 2S connected to a first port; a second TLS having a 1S connected to the first port and having a 2S connected to a second port; a third TLS having a 1S connected to the second port and having a 2S connected to the third port; a first cancellation path (CP) that is connected between the first port and the third port and introduces a current that is 90 degrees out of phase with a first voltage at the first port; and a second CP that is connected between the second port and the third port and introduces a current that is orthogonal to the current introduces by the first CP.
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公开(公告)号:WO2020036669A2
公开(公告)日:2020-02-20
申请号:PCT/US2019/036628
申请日:2019-06-11
Inventor: NAGULU, Aravind , KRISHNASWAMY, Harish
IPC: H03B5/30
Abstract: A circulator, comprising: a gyrator having a first side (1S) and a second side (2S) connected to a third port; a first transmission line section (TLS) having a 1 S connected to the 1 S of the gyrator and a 2S connected to a first port; a second TLS having a 1S connected to the first port and having a 2S connected to a second port; a third TLS having a 1S connected to the second port and having a 2S connected to the third port; a first cancellation path (CP) that is connected between the first port and the third port and introduces a current that is 90 degrees out of phase with a first voltage at the first port; and a second CP that is connected between the second port and the third port and introduces a current that is orthogonal to the current introduces by the first CP.
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公开(公告)号:WO2020010247A1
公开(公告)日:2020-01-09
申请号:PCT/US2019/040588
申请日:2019-07-03
Applicant: DEO, Anand
Inventor: DEO, Anand
Abstract: Localized heating can be provided using fixed-frequency planar transmission line resonators arranged along a main-line, and tuning an electromagnetic input signal frequency applied to the main line to selectively address and energize one or more planar resonators for also addressing and energizing one or more correspondingly located active substrate transducer heat sources for depositing heat in an adjacent active substrate. More generally, adjusting input signal frequency to select one or more planar resonators arranged along a main line can be used to selectively address and energize an electromagnetic-to-heat, an electromagnetic-to-vibration, or other transducer to controllably direct energy toward a desired transducer load.
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公开(公告)号:WO2019231774A1
公开(公告)日:2019-12-05
申请号:PCT/US2019/033403
申请日:2019-05-21
Applicant: SPEEDLINK TECHNOLOGY INC.
Inventor: JUNG, Doohwan , CHEN, Thomas , WANG, Hua
Abstract: According to one embodiment, a dual voltage controlled oscillator (VCO) circuit includes a first VCO and a second VCO. The first VCO includes: a first variable capacitor having an input node, a first output node, and a second output node, a second variable capacitor coupled in parallel with the first variable capacitor, a first transistor, and a second transistor, where the first transistor has a first drain coupled to the first output node, a first gate coupled to the second output node, and a first source coupled to a ground, where the second transistor has a second drain coupled to the second output node and a second gate coupled to the first output node, and a second source coupled to the ground. The dual VCO circuit includes a second VCO mirroring the first VCO, a first and a second inductors coupled to the first and the second VCO respectively.
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公开(公告)号:WO2019223087A1
公开(公告)日:2019-11-28
申请号:PCT/CN2018/096025
申请日:2018-07-17
Applicant: 深圳市兴汇科技有限公司
Abstract: 一种利用权电阻网络配合FPGA实现精准的波形输出的电路,包括第一权电阻网络、第二权电阻网络、第一电压跟随电路、第二电压跟随电路和芯片U2,所述第一权电阻网络和第二权电阻网络均与芯片U2电连接,第一电压跟随电路接第一权电阻网络的输出端,第二电压跟随电路接第二权电阻网络的输出端。该电路利用权电阻网络配合FPGA实现精准的波形输出,通过FPGA的接口IO1-接口IO8引脚的不同值,可以在A点输出256种不同的电压(以3.3V为参考电压),通过第一权电阻网络或第二权电阻网络搭配FPGA实现低成本的波形输出和高精度的频率控制,且每八个FPGA的接口IO就能实现一组波形输出,可实现多路的波形输出且互不干扰。
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公开(公告)号:WO2019215522A1
公开(公告)日:2019-11-14
申请号:PCT/IB2019/053027
申请日:2019-04-12
Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION , IBM UNITED KINGDOM LIMITED , IBM (CHINA) INVESTMENT COMPANY LIMITED
Inventor: BAUGHMAN, Aaron , COX, Aaron , HAMMER, Stephen , KENT, John, Joseph
IPC: H03B11/00
Abstract: A reflection is captured of a subsonic signal reflected by a contact surface. The contact surface is contacting a simulated surface of an object projected from a midair interface (MAI) device. A difference between the subsonic signal and the reflection is converted into a measurement of a flow in the contact surface. When the measurement is in a range of measurements, a change is caused in a temperature of a volume of a medium, the simulated surface being projected in volume of the medium, where the change in the temperature causes a second change in the flow in the contact surface.
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公开(公告)号:WO2019208675A1
公开(公告)日:2019-10-31
申请号:PCT/JP2019/017545
申请日:2019-04-25
Applicant: パナソニックIPマネジメント株式会社
IPC: H03B5/18
Abstract: 発振周波数の調整作業の難易度を下げやすい発振装置、及び発振周波数の調整方法を提供する。発振装置(1)は、増幅回路(3)と、帰還回路(4)と、を備える。増幅回路(3)は、入力端子(31)に入力された信号を増幅して出力端子(32)から出力する。帰還回路(4)は、出力端子(32)と入力端子(31)との間に電気的に接続されている。帰還回路(4)は、共振器(2)と、第1伝送線路(41)と、第2伝送線路(42)と、を有する。第1伝送線路(41)は、出力端子(32)と共振器(2)との間に電気的に接続されている。第2伝送線路(42)は、入力端子(31)と共振器(2)との間に電気的に接続されている。発振装置(1)は、調整部(5)を更に備える。調整部(5)は、第1伝送線路(41)及び第2伝送線路(42)の少なくとも一方からなる対象線路について長さ及び特性インピーダンスの少なくとも一方を調整する。
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公开(公告)号:WO2019188675A1
公开(公告)日:2019-10-03
申请号:PCT/JP2019/011748
申请日:2019-03-20
Applicant: 株式会社大真空
Inventor: 吉岡 宏樹
IPC: H03B5/32
Abstract: 複数の外部接続端子及び複数の実装用電極を有する圧電振動子と、複数の実装用電極に接続される複数の実装端子を有して、圧電振動子に実装される集積回路素子とを備え、外部接続端子に接続されている実装用電極の少なくとも1つの実装用電極は、集積回路素子の実装領域において、集積回路素子の実装端子よりも内方まで延出されている配線パターンを有している。
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