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    DYNAMICALLY CONFIGURABLE AND RE-CONFIGURABLE DATA PATH
    41.
    发明申请
    DYNAMICALLY CONFIGURABLE AND RE-CONFIGURABLE DATA PATH 审中-公开
    动态配置和可配置的数据路径

    公开(公告)号：WO2008131143A2

    公开(公告)日：2008-10-30

    申请号：PCT/US2008/060696

    申请日：2008-04-17

    Applicant: CYPRESS SEMICONDUCTOR CORPORATION ,  SNYDER, Warren ,  SULLAM, Bert

    Inventor： SNYDER, Warren ,  SULLAM, Bert

    IPC: G06F9/302

    CPC classification number: H03K19/177

    Abstract: An apparatus includes a configuration memory coupled to one or more structural arithmetic elements, the configuration memory to store values that cause the structural arithmetic elements to perform various functions. The apparatus also includes a system controller to dynamically load the configuration memory with values, and to prompt the structural arithmetic elements to perform functions according to the values stored by the configuration memory.

    Abstract translation: 一种装置包括耦合到一个或多个结构运算元件的配置存储器，该配置存储器存储导致结构运算元件执行各种功能的值。 该装置还包括系统控制器，用于使用值动态地加载配置存储器，并且提示结构运算元件根据配置存储器存储的值来执行功能。

    UNIVERSAL DIGITAL BLOCK WITH INTEGRATED ARITHMETIC LOGIC UNIT
    42.
    发明申请
    UNIVERSAL DIGITAL BLOCK WITH INTEGRATED ARITHMETIC LOGIC UNIT 审中-公开
    通用数字块与集成算术逻辑单元

    公开(公告)号：WO2008131138A2

    公开(公告)日：2008-10-30

    申请号：PCT/US2008/060685

    申请日：2008-04-17

    Applicant: CYPRESS SEMICONDUCTOR CORPORATION ,  SNYDER, Warren ,  SULLAM, Bert

    Inventor： SNYDER, Warren ,  SULLAM, Bert

    IPC: G06F9/02 ,  G06F13/14

    CPC classification number: H03K19/177

    Abstract: An array of universal digital blocks include programmable logic device sections that have uncommitted user programmable logic functions and structural datapath sections that include dedicated and highly configurable arithmetic operators. A routing channel matrix programmably connects to different programmable logic device sections and datapath sections in the different universal digital blocks.

    Abstract translation: 一组通用数字模块包括具有未提交的用户可编程逻辑功能的可编程逻辑器件部分和包括专用和高度可配置的算术运算符的结构数据通路部分。 路由信道矩阵可编程地连接到不同通用数字块中的不同可编程逻辑器件部分和数据路径部分。

    LOGIC ARRAY DEVICES HAVING COMPLEX MACRO-CELL ARCHITECTURE AND METHODS FACILITATING USE OF SAME
    44.
    发明申请
    LOGIC ARRAY DEVICES HAVING COMPLEX MACRO-CELL ARCHITECTURE AND METHODS FACILITATING USE OF SAME 审中-公开
    具有复杂宏小结构的逻辑阵列设备及其使用方法

    公开(公告)号：WO2004001803A3

    公开(公告)日：2005-02-17

    申请号：PCT/US0319478

    申请日：2003-06-19

    Applicant: VIASIC INC ,  COX WILLIAM D

    Inventor： COX WILLIAM D

    IPC: H03K19/173 ,  H03K19/0185

    CPC classification number: H03K19/1733 ,  H03K19/1735 ,  H03K19/177 ,  H03K19/17728 ,  H03K19/17796

    Abstract: Logic array devices having complex macro-cell architecture and methods facilitating use of same. A semiconductor device comprising an array of logic cells and programmable metal includes gate structures that are pre-wired, where, inputs and/or outputs are available for routing in programmable metal, possibly as part of a hybrid process. The device can also include selectable, in-line inverters, which can share the input/output tracks with logic inputs. A bubble-pushing algorithm can take ad-vantage of the selectable in-line inverters to reduce the number of inverters in a de-sign. In some embodiments, an embedded clock line is common to a plurality of logic cells. The clock line is terminated in a clock cell, which can include test logic, so that a clock group is formed. Flexibility to power down cells, or groups of cells can be provided by power traces with programmable connections.

    Abstract translation: 逻辑阵列器件具有复杂的宏单元结构和便于使用它们的方法。 包括逻辑单元和可编程金属阵列的半导体器件包括预先布线的栅极结构，其中输入和/或输出可用于可编程金属中的布线，可能是混合工艺的一部分。 该器件还可以包括可选择的在线逆变器，其可以与逻辑输入共享输入/输出轨道。 气泡推动算法可以获得可选择的在线逆变器的优势，以减少去除符号中的逆变器数量。 在一些实施例中，嵌入式时钟线对于多个逻辑单元是公用的。 时钟线在时钟单元中终止，时钟单元可以包括测试逻辑，从而形成时钟组。 可以通过具有可编程连接的电源轨迹提供对电池或电池组断电的灵活性。

    METHOD AND DEVICES FOR TREATING AND/OR PROCESSING DATA
    46.
    发明申请
    METHOD AND DEVICES FOR TREATING AND/OR PROCESSING DATA 审中-公开
    用于数据处理和/或处理的方法和设备

    公开(公告)号：WO02071249A8

    公开(公告)日：2003-10-30

    申请号：PCT/EP0202403

    申请日：2002-03-05

    Applicant: PACT INF TECH GMBH ,  VORBACH MARTIN ,  BAUMGARTE VOLKER ,  NUECKEL ARMIN DR ,  MAY FRANK

    Inventor： VORBACH MARTIN ,  BAUMGARTE VOLKER ,  NUECKEL ARMIN DR ,  MAY FRANK

    IPC: G06F7/00 ,  G06F1/08 ,  G06F1/10 ,  G06F1/32 ,  G06F5/06 ,  G06F9/54 ,  G06F15/78 ,  G06F15/80 ,  H03K19/177

    CPC classification number: G06F8/447 ,  G06F15/7867 ,  H03K19/177

    Abstract: The invention relates to procedures and methods for administering and transferring data within multi-dimensional systems consisting of transmitters and receivers. The division of a data stream into several independent branches and the subsequent combination sequential collection of the individual branches to form a data stream can be carried out in a simple manner. The individual data streams are re-combined in a correct time sequence. Said inventive method is particularly useful for processing re-entrant codes and is suitable for configurable architectures wherein efficient control of the configuration and reconfiguration is highly important.

    Abstract translation: 本发明描述了用于管理和发送发射机和接收机的多维阵列内的数据的方法和方法。 将数据流分成几个独立的分支以及将各个分支随后组合成数据流应该容易实现，各个数据流再次以正确的时间顺序组合。 这种方法对于处理可重入代码特别重要。 所描述的方法特别适用于可配置体系结构，配置和重新配置的有效控制引起了特别的关注。

    FIELD PROGRAMMABLE GATE ARRAY WITH DISTRIBUTED GATE-ARRAY FUNCTIONALITY
    47.
    发明申请
    FIELD PROGRAMMABLE GATE ARRAY WITH DISTRIBUTED GATE-ARRAY FUNCTIONALITY 审中-公开
    具有分布式门阵列功能的现场可编程门阵列

    公开(公告)号：WO1998039843A1

    公开(公告)日：1998-09-11

    申请号：PCT/US1997015376

    申请日：1997-08-28

    Applicant: XILINX, INC.

    Inventor： XILINX, INC. ,  NEW, Bernard, J.

    IPC: H03K19/177

    CPC classification number: H03K19/177 ,  H03K19/17704

    Abstract: A field programmable gate array (FPGA) having a plurality of configurable logic blocks (CLBs). Each of the CLBs includes programmable interconnect resources, a field programmable configurable logic element (CLE) circuit and a corresponding non-field programmable gate array. The programmable interconnect resources are programmed to selectively couple or decouple each CLE circuit from its corresponding non-field programmable gate array. Dedicated interconnect resources enable adjacent non-field programmable gate arrays to be coupled. By coupling adjacent non-field programmable gate arrays, one or more relatively large non-field programmable gate arrays can be formed. The non-field programmable gate arrays have a greater logic density than the CLE circuits, thereby providing an improved logic density to the CLBs. Moveover, because each CLB includes a non-field programmable gate array, each of the CLE circuits is readily connectable to a non-field programmable gate array. The non-field programmable gate array can be used to provide a plurality of mask-programmable input/output driver circuits for connection to the pads of the FPGA.

    Abstract translation: 具有多个可配置逻辑块（CLB）的现场可编程门阵列（FPGA）。 每个CLB包括可编程互连资源，现场可编程可配置逻辑元件（CLE）电路和相应的非现场可编程门阵列。 可编程互连资源被编程为选择性地将每个CLE电路与其对应的非现场可编程门阵列耦合或去耦合。 专用互连资源使相邻的非现场可编程门阵列耦合。 通过耦合相邻的非现场可编程门阵列，可以形成一个或多个相对较大的非场可编程门阵列。 非现场可编程门阵列具有比CLE电路更大的逻辑密度，从而为CLB提供改进的逻辑密度。 移动，因为每个CLB包括非现场可编程门阵列，每个CLE电路可以容易地连接到非现场可编程门阵列。 非现场可编程门阵列可用于提供用于连接到FPGA的焊盘的多个掩模可编程输入/输出驱动器电路。

    SCHOTTKY-CMOS ASYNCHRONOUS LOGIC CELLS
    50.
    发明申请
    SCHOTTKY-CMOS ASYNCHRONOUS LOGIC CELLS 审中-公开

    公开(公告)号：WO2018191217A1

    公开(公告)日：2018-10-18

    申请号：PCT/US2018/026817

    申请日：2018-04-10

    Applicant: SCHOTTKY LSI, INC.

    Inventor： CHANG, Augustine, Wei-Chun ,  DERMY, Pierre

    IPC: H03K19/0956 ,  H03K19/017 ,  H03K19/177 ,  H03K19/0948

    CPC classification number: H03K19/0956 ,  H03K19/017 ,  H03K19/0948 ,  H03K19/177

    Abstract: Integrated circuits described herein implement an x-input logic gate. The integrated circuit includes a plurality of Schottky diodes that includes x Schottky diodes and a plurality of source-follower transistors that includes x source-follower transistors. Each respective source-follower transistor of the plurality of source-follower transistors includes a respective gate node that is coupled to a respective Schottky diode. A first source-follower transistor of the plurality of source-follower transistors is connected serially to a second source-follower transistor of the plurality of source-follower transistors.

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