公开(公告)号：WO2005034175A3

公开(公告)日：2005-12-15

申请号：PCT/US2004024362

申请日：2004-07-28

申请人： ACTEL CORP ,  BAKKER GREGORY ,  EL-AYAT KHALED ,  SPEERS THEODORE ,  ZHU LIMIN ,  SCHUBERT BRIAN ,  BALASUBRAMANIAN RABINDRANATH ,  KOLKIND KURT ,  BARRAZA THOMAS F ,  NARAYANAN VENKATESH ,  MCCOLLUM JOHN ,  PLANTS WILLIAM C

发明人： BAKKER GREGORY ,  EL-AYAT KHALED ,  SPEERS THEODORE ,  ZHU LIMIN ,  SCHUBERT BRIAN ,  BALASUBRAMANIAN RABINDRANATH ,  KOLKIND KURT ,  BARRAZA THOMAS F ,  NARAYANAN VENKATESH ,  MCCOLLUM JOHN ,  PLANTS WILLIAM C

IPC分类号： H01L20060101 ,  H03K19/177

CPC分类号： H03K19/1776 ,  G01K7/015 ,  G06F1/08 ,  G06F1/28 ,  G06F1/30 ,  G06F15/7842 ,  G06F15/7867 ,  H03F3/45475 ,  H03F2203/45136 ,  H03F2203/45166 ,  H03K17/223 ,  H03K19/177 ,  H03K19/17732

摘要： A programmable system-on-a-chip integrated circuit device comprises a programmable logic block (12), a non-volatile memory block (14), an analog sub-system (16), an analog input/output circuit block (22), and a digital input/output circuit block 20. A programmable interconnect architecture (Fig. 2) includes programmable elements and interconnect conductors. Ones of the programmable elements are coupled to the programmable logic block, the non-volatile memory block, the analog sub-system, the analog input/output circuit block, the digital input/output circuit block, and to the interconnect conductors, such that inputs and outputs of the programmable logic block, the non-volatile memory block, the analog sub-system, the analog input/output circuit block, and the digital input/output circuit block can be programmably coupled to one another.

摘要翻译： 一种可编程片上系统集成电路装置，包括可编程逻辑块（12），非易失性存储块（14），模拟子系统（16），模拟输入/输出电路块（22） 和数字输入/输出电路块20.可编程互连架构（图2）包括可编程元件和互连导体。 可编程元件的一部分耦合到可编程逻辑块，非易失性存储器块，模拟子系统，模拟输入/输出电路块，数字输入/输出电路块和互连导体，使得 可编程逻辑块，非易失性存储器块，模拟子系统，模拟输入/输出电路块和数字输入/输出电路块的输入和输出可以可编程地彼此耦合。

公开(公告)号：WO2006039254A3

公开(公告)日：2006-04-13

申请号：PCT/US2005/034526

申请日：2005-09-26

申请人： ACTEL CORPORATION ,  SPEERS, Theodore

发明人： SPEERS, Theodore

IPC分类号： H01L23/48

摘要： An integrated circuit system includes a first set of integrated circuit dice each member of the set having a different configuration of input/output circuits disposed thereon and a second set of integrated circuit dice each having different logical function circuits disposed thereon. Each member of the first and second sets of integrated circuit dice include an array of face-to-face bonding pads disposed thereon that mate with the array of face-to­face bonding pads of each member of the other set.

公开(公告)号：WO2006071570A2

公开(公告)日：2006-07-06

申请号：PCT/US2005045620

申请日：2005-12-15

申请人： ACTEL CORP ,  SPEERS THEODORE

发明人： SPEERS THEODORE

IPC分类号： H03K19/173

CPC分类号： H03K19/17776 ,  H03K19/17756 ,  H03K19/17772

摘要： A non-volatile memory configuration scheme is disclosed for volatile-memory-based programmable circuits in a programmable integrated circuit that includes an FPGA fabric, a plurality of first configurable circuit elements external to the FPGA fabric, and a plurality of second configurable circuit elements external to the FPGA fabric. A plurality of distributed configuration non-volatile memory cells is disposed in the FPGA, each one of the distributed configuration non-volatile memory cells coupled to a different one of the plurality of first configurable circuit elements. A non-volatile memory array stores, configuration information for the second configurable circuit elements. A plurality of register cells is disposed with the second configurable circuit elements and is coupleable to the non-volatile memory array, each one of the register cells coupled to a different one of the plurality of second configurable circuit elements.

摘要翻译： 公开了一种用于可编程集成电路中的基于易失性存储器的可编程电路的非易失性存储器配置方案，该可编程集成电路包括FPGA结构，FPGA结构外部的多个第一可配置电路元件以及外部的多个第二可配置电路元件 到FPGA架构。 多个分布式配置非易失性存储单元被布置在FPGA中，每个分布式配置非易失性存储单元耦合到多个第一可配置电路元件中的不同的一个。 非易失性存储器阵列存储用于第二可配置电路元件的配置信息。 多个寄存器单元与第二可配置电路元件一起布置并且可耦合到非易失性存储器阵列，每个寄存器单元耦合到多个第二可配置电路元件中的不同的一个。

公开(公告)号：WO2006039254A2

公开(公告)日：2006-04-13

申请号：PCT/US2005034526

申请日：2005-09-26

申请人： ACTEL CORP ,  SPEERS THEODORE

发明人： SPEERS THEODORE

IPC分类号： H01L23/48

CPC分类号： H01L25/18 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16145 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2924/00014 ,  H03K19/17732 ,  H03K19/17744 ,  H03K19/17796 ,  H01L2224/05599

摘要： An integrated circuit system includes a first set of integrated circuit dice each member of the set having a different configuration of input/output circuits disposed thereon and a second set of integrated circuit dice each having different logical function circuits disposed thereon. Each member of the first and second sets of integrated circuit dice include an array of face-to-face bonding pads disposed thereon that mate with the array of face-to­face bonding pads of each member of the other set.

摘要翻译： 集成电路系统包括第一组集成电路芯片，该组件的每个部件具有设置在其上的输入/输出电路的不同配置，以及每组具有布置在其上的不同逻辑功能电路的第二组集成电路芯片。 第一和第二组集成电路芯片的每个部件包括与其上的每个部件的面对接焊盘的阵列相配合的面对面焊盘的阵列。

公开(公告)号：WO2010071847A1

公开(公告)日：2010-06-24

申请号：PCT/US2009/068856

申请日：2009-12-18

申请人： ACTEL CORPORATION ,  SPEERS, Theodore

发明人： SPEERS, Theodore

IPC分类号： H03K19/177

CPC分类号： H03K19/17772 ,  H03K19/17784

摘要： A programmable logic device (PLD) adapted to enter a low-power or sleep mode with programmable wakeup pins in a wakeup group of pins is disclosed. Wake on a single pin change, wake on vector, and wake on a single pin transition are supported. The approach is to select the actively participating pins, enable the desired operation, define the wakeup condition, enter sleep mode, monitor the external signals coupled to the active pins, and exit sleep mode when the wakeup condition is detected.

摘要翻译： 公开了一种可编程逻辑器件（PLD），其适于在唤醒组引脚中进入具有可编程唤醒引脚的低功率或睡眠模式。 唤醒单个引脚更改，唤醒向量，并在单引脚转换唤醒被支持。 该方法是选择主动参与的引脚，启用所需的操作，定义唤醒条件，进入睡眠模式，监控耦合到活动引脚的外部信号，并在检测到唤醒条件时退出休眠模式。

公开(公告)号：WO2006071570A3

公开(公告)日：2006-07-06

申请号：PCT/US2005/045620

申请日：2005-12-15

申请人： ACTEL CORPORATION ,  SPEERS, Theodore

发明人： SPEERS, Theodore

IPC分类号： H03K19/173

摘要： A non-volatile memory configuration scheme is disclosed for volatile-memory-based programmable circuits in a programmable integrated circuit that includes an FPGA fabric, a plurality of first configurable circuit elements external to the FPGA fabric, and a plurality of second configurable circuit elements external to the FPGA fabric. A plurality of distributed configuration non-volatile memory cells is disposed in the FPGA, each one of the distributed configuration non-volatile memory cells coupled to a different one of the plurality of first configurable circuit elements. A non-volatile memory array stores, configuration information for the second configurable circuit elements. A plurality of register cells is disposed with the second configurable circuit elements and is coupleable to the non-volatile memory array, each one of the register cells coupled to a different one of the plurality of second configurable circuit elements.

公开(公告)号：WO2005034175A2

公开(公告)日：2005-04-14

申请号：PCT/US2004/024362

申请日：2004-07-28

申请人： ACTEL CORPORATION ,  BAKKER, Gregory ,  EL-AYAT, Khaled ,  SPEERS, Theodore ,  ZHU, Limin ,  SCHUBERT, Brian ,  BALASUBRAMANIAN, Rabindranath ,  KOLKIND, Kurt ,  BARRAZA, Thomas, F. ,  NARAYANAN, Venkatesh ,  MCCOLLUM, John ,  PLANTS, William, C.

发明人： BAKKER, Gregory ,  EL-AYAT, Khaled ,  SPEERS, Theodore ,  ZHU, Limin ,  SCHUBERT, Brian ,  BALASUBRAMANIAN, Rabindranath ,  KOLKIND, Kurt ,  BARRAZA, Thomas, F. ,  NARAYANAN, Venkatesh ,  MCCOLLUM, John ,  PLANTS, William, C.

IPC分类号： H01L

CPC分类号： H03K19/1776 ,  G01K7/015 ,  G06F1/08 ,  G06F1/28 ,  G06F1/30 ,  G06F15/7842 ,  G06F15/7867 ,  H03F3/45475 ,  H03F2203/45136 ,  H03F2203/45166 ,  H03K17/223 ,  H03K19/177 ,  H03K19/17732

摘要： A programmable system-on-a-chip integrated circuit device comprises a programmable logic block, a non-volatile memory block, an analog sub-system, an analog input/output circuit block, and a digital input/output circuit block. A programmable interconnect architecture includes programmable elements and interconnect conductors. Ones of the programmable elements are coupled to the programmable logic block, the non­volatile memory block, the analog sub-system, the analog input/output circuit block, the digital input/output circuit block, and to the interconnect conductors, such that inputs and outputs of the programmable logic block, the non-volatile memory block, the analog sub­system, the analog input/output circuit block, and the digital input/output circuit block can be programmably coupled to one another.

摘要翻译： 一种可编程片上系统集成电路装置，包括可编程逻辑块，非易失性存储块，模拟子系统，模拟输入/输出电路块和数字输入/输出电路块。 可编程互连架构包括可编程元件和互连导体。 可编程元件的一部分耦合到可编程逻辑块，非易失性存储块，模拟子系统，模拟输入/输出电路块，数字输入/输出电路块和互连导体，使得输入和 可编程逻辑块，非易失性存储器块，模拟子系统，模拟输入/输出电路块和数字输入/输出电路块的输出可以可编程地彼此耦合。