-
公开(公告)号：WO2008027066A2
公开(公告)日：2008-03-06
申请号：PCT/US2006060093
申请日：2006-10-20
Applicant: MONTAGE TECHNOLOGY GROUP LTD , SI XIAOMIN , WU LARRY
Inventor： SI XIAOMIN , WU LARRY
IPC: H03D3/24
CPC classification number: H04L7/0337 , H03L7/0814 , H04L7/0004 , H04L7/0041
Abstract: A data and clock recovery circuit having a retimer mode and a resync mode. In one embodiment, a receiver circuit includes: a retimer; a clock recovery circuit to provide a clock signal to the retimer; and an adjustable delay to provide a delayed version of an input signal to the retimer. When in a resync mode, the adjustable delay causes a pre-selected delay in the input signal and the clock recovery circuit dynamically selects a clock phase to generate the clock signal. When in a second mode, the adjustable delay dynamically adjusts the delayed version of the input signal and the clock recovery circuit outputs the clock signal having a pre-selected clock phase.
Abstract translation: 一种具有重定时器模式和重新同步模式的数据和时钟恢复电路。 在一个实施例中，接收机电路包括：重定时器; 时钟恢复电路，用于向重定时器提供时钟信号; 以及可调延迟，以向延迟器提供输入信号的延迟版本。 当处于重新同步模式时，可调节延迟导致输入信号中预先选择的延迟，并且时钟恢复电路动态地选择时钟相位以产生时钟信号。 当处于第二模式时，可调延迟动态地调节输入信号的延迟版本，并且时钟恢复电路输出具有预选时钟相位的时钟信号。
-
公开(公告)号：WO2006030904A1
公开(公告)日：2006-03-23
申请号：PCT/JP2005/017165
申请日：2005-09-16
CPC classification number: H04L7/0012 , G06F1/12 , H04L7/0041
Abstract: 【課題】 各コアが設定できるクロック周波数の自由度が大きく、動作が決定的(deterministic)で、通信レイテンシが小さく、信頼性の高い、コア間の通信ができる技術を提供することにある。又、本発明の目的は、半導体装置内の通信履歴から半導体装置の性能に影響を与える要因を解析し、次世代の半導体装置に反映させることにより、信頼性の高い半導体装置を提供することにある。 【解決手段】 本発明の半導体装置は、クロック信号clkAに同期してデータを送信するコアＡと、ある一定の周期でクロック信号clkAの立ち上がり又は立ち下がりと一致するクロック信号clkBに同期してデータ受信するコアＢと、コアＡとコアＢとの間の通信を制御する制御部とを有する。制御部は、クロック信号clkBのセットアップより前に到着するデータのみをコアＢが受信できるように制御する。更に、コア間の通信状況を履歴保存する。
Abstract translation: 为了提供能够实现核心通信能够建立的时钟频率的灵活性的核心间通信的技术，操作是确定性的，通信等待时间小，可靠性高。 本发明的目的是通过从半导体器件的通信历史中分析影响那些半导体器件性能的因素，然后将这种分析反映到下一代的半导体器件，来提供高可靠性的半导体器件。 解决问题的手段本发明的半导体器件具有与时钟信号（clkA）同步发送数据的核心A，与与上升或下降一致的时钟信号（clkB）同步地接收数据的核心B 时钟信号（clkA）的边沿，以及控制核心A和B之间的通信的控制部分。控制部分控制核心B可以仅接收在建立时钟信号之前到达的数据 （CLKB）。 而且，它存储了核心间通信状态的历史。
-
公开(公告)号：WO2004047333A2
公开(公告)日：2004-06-03
申请号：PCT/CA2003/001747
申请日：2003-11-18
Applicant: TENXC WIRELESS , WU, Shiquan , LITVA, John
Inventor： WU, Shiquan , LITVA, John
IPC: H04B7/06
CPC classification number: H04W16/28 , H01Q1/246 , H01Q3/2605 , H01Q21/08 , H04B7/0408 , H04B7/0617 , H04B7/086 , H04B7/2662 , H04J3/0682 , H04L7/0041 , H04W24/00 , H04W52/42 , H04W56/0045 , H04W88/08
Abstract: A method of beam forming is provided for an appliqué intelligent antenna system. The appliqué system uses a watchdog function to monitor broadcast channels of an existing mobile wireless base station to which it is attached. The appliqué system synchronizes itself in frequency and time to the base station. In GSM timing delays are used to prevent collision of timeslots from various mobile terminals. The appliqué system uses this time delay mechanism to compensate for its own processing delays so that its presence is transparent to the existing base station. Angle of arrival calculations are made to determining beamforming parameters. The antenna of the four element antenna system are separated by is (5 1/2 _ 1)/2 times the wavelength. Angle of arrival for the strongest uplink multipath signal are used to direct the downlink beam.
Abstract translation: 提供了一种用于贴布式智能天线系统的波束形成方法。 贴花系统使用看门狗功能来监视其所连接的现有移动无线基站的广播信道。 贴花系统在频率和时间上与基站同步自身。 在GSM中，定时延迟用于防止来自各种移动终端的时隙的冲突。 贴花系统使用这种延时机制来补偿其自身的处理延迟，使其存在对现有基站是透明的。 进行角度计算是为了确定波束成形参数。 四元天线系统的天线与波长的（5 1/2/1）/ 2倍分开。 用于最强上行多径信号的到达角用于引导下行链路波束。
-
公开(公告)号：WO03052975A3
公开(公告)日：2003-08-07
申请号：PCT/EP0214151
申请日：2002-12-12
Applicant: SCHOTT GLAS , ZEISS STIFTUNG
Inventor： TATAH KARIM , BONJA JEFFREY A , ROBINSON MATTHEW SCOTT , STRACK RICHARD
CPC classification number: H04B10/25 , H04L7/0041
Abstract: A method to skew or deskew a plurality of optical channels in a multichannel optical cable which includes the steps of determining an optical pulse transmission time in at least at first channel and a second channel of the multichannel optical cable. A relative pulse delay between the first channel and the second channel of the multi-channel optical cable is calculated. Delay optics with the appropriate relative pulse delay are serially optically connected to at least one of the channels to one of skew or deskew the first channel relative to the second channel.
Abstract translation: 一种使多信道光缆中的多个光信道歪斜或歪斜的方法，该方法包括至少在多信道光缆的第一信道和第二信道中确定光脉冲传输时间的步骤。 计算多通道光缆的第一通道和第二通道之间的相对脉冲延迟。 具有适当的相对脉冲延迟的延迟光学器件被串行地光学连接到至少一个通道，以使第一通道相对于第二通道偏斜或偏斜之一。
-
公开(公告)号：WO2003055094A1
公开(公告)日：2003-07-03
申请号：PCT/DK2001/000858
申请日：2001-12-20
Applicant: AMIN, Bhavik
Inventor： AMIN, Bhavik
IPC: H04B3/50
CPC classification number: H04L25/14 , H04L7/0004 , H04L7/0041 , H04N7/108
Abstract: It should be noted that automatic delay setting according to the invention is extremely advantageous in a typical KVM environment since KVM installation is typically performed by a person skilled within the field of computer hardware. However, it is not very likely that such a person is able to perform manual calibration if such calibration, when being performed manually, requires skills within the filed of analogue transmission. According to the invention, standard data transmission cables may be applied for KVM-extending purposes, thereby avoiding the need for new dedicated wiring by means of special cables, e.g. COAX, having the desired analogue transmission properties. Evidently, this is of great importance since standard data transmission cables are typically the only kind of cable available at the premises. Another advantage is the relatively low price of structurel cabling (another word for data transmission cabling or cat5/cat6) compared to for example coax.
Abstract translation: 应当注意，根据本发明的自动延迟设置在典型的KVM环境中是非常有利的，因为KVM安装通常由计算机硬件领域的技术人员执行。 然而，如果这样的校准在手动执行时需要在模拟传输领域中的技能，则这样的人不太可能执行手动校准。 根据本发明，标准数据传输电缆可以用于KVM扩展目的，从而避免了通过特殊电缆例如新的专用布线的需要。 COAX，具有所需的模拟传输特性。 显然，这是非常重要的，因为标准数据传输电缆通常是在场所可用的唯一电缆。 另一个优点是与例如同轴电缆相比，结构布线（数据传输布线或cat5 / cat6的另一个字）的价格相对较低。
-
Patent Agency Ranking46.发明申请
公开(公告)号：WO01050664A3
公开(公告)日：2002-01-31
申请号：PCT/DE2000/004545
申请日：2000-12-19
IPC: H04B10/04 , H04B10/06 , H04B10/142 , H04B10/152 , H04J3/06 , H04J14/08 , H04L7/00 , H04L7/02
CPC classification number: H04J14/08 , H04L7/0041 , H04L7/0075
Abstract: The invention relates to a method for synchronising the phase of two RZ data signals (RZS1, RZS2) which have been combined to form one time multiplex signal (MS1). According to said method, the power of half a fundamental wave of the multiplex signal (MS1) is measured and the phase differential is regulated in such a way that the power of the wave reaches a minimum.
Abstract translation: 概括为两个相位同步到一个时分复用信号（MS1）的RZ数据信号（RZS1，RZS2）多路复用信号的半基波的性能（MS1）进行测量和调节，即其功率取最小值的相位差。
-
公开(公告)号：WO0117128A3
公开(公告)日：2001-09-07
申请号：PCT/US0023951
申请日：2000-08-30
Applicant: QUALCOMM INC
Inventor： VEROLI MAURIZIO DI , BAR-DAVID AYAL
CPC classification number: H04L7/0029 , H04B7/2125 , H04L7/0041
Abstract: A method for generating a variable delay of a signal (28), including: providing a clock (50) indicating a sequence of sample times at regular intervals and receiving a sequence of input samples (41) representing input values of the signal at respective sample times indicated by the clock. The method further includes determining the delay (40, 46) with a temporal resolution substantially finer than the clock interval to be applied to the signal at each of the respective sample times. For each of the sample times, responsive to the respectively-determined delay, one or more of the input samples are processed so as to generate a corresponding output sample (43) representing a delayed output value of the signal at the sample time.
Abstract translation: 一种用于产生信号（28）的可变延迟的方法，包括：以规则间隔提供指示采样时间序列的时钟（50），并且接收表示在相应采样处的信号输入值的输入采样序列（41） 时钟指示的时间。 该方法进一步包括以时间分辨率确定延迟（40,46），该时间分辨率比在各个采样时间中的每个采样时间对信号施加的时钟间隔要精确得多。 对于每个采样时间，响应于分别确定的延迟，对一个或多个输入采样进行处理，以便生成表示采样时间处信号的延迟输出值的对应输出采样（43）。
-
公开(公告)号：WO2015167745A1
公开(公告)日：2015-11-05
申请号：PCT/US2015/024000
申请日：2015-04-02
Applicant: SCHWEITZER ENGINEERING LABORATORIES, INC.
Inventor： RICE, Raymond W. , ACHANTA, Srinivas
IPC: H04J3/06
CPC classification number: H04L7/0041 , H04J3/0635 , H04J3/0682
Abstract: Disclosed herein are a variety of systems and methods for correcting for propagation delay in time signals used in connection with an electric power generation and delivery system. According to various embodiments, a device consistent with the present disclosure may determine an estimated propagation delay between an accurate time source and a receiving device. The propagation delay may be determined based on a variety of transmission parameters including, for example, communication channel type and/or length. A corrected time signal may be generated by advancing a reference incitation such as an "on-time" reference and/or "start-of-second" reference included in the time signal by an amount associated with the propagation delay. The corrected time signal may then be transmitted to the receiving device.
Abstract translation: 这里公开了用于校正与发电和输送系统相关联的时间信号中的传播延迟的各种系统和方法。 根据各种实施例，与本公开一致的设备可以确定精确时间源和接收设备之间的估计传播延迟。 可以基于包括例如通信信道类型和/或长度的各种传输参数来确定传播延迟。 可以通过将包括在时间信号中的诸如“准时”参考和/或“起始”参考的参考煽动与传播延迟相关联的量来产生校正的时间信号。 然后可以将校正的时间信号发送到接收装置。
-
49.发明申请
公开(公告)号：WO2015112321A1
公开(公告)日：2015-07-30
申请号：PCT/US2015/010086
申请日：2015-01-05
Applicant: QUALCOMM INCORPORATED
Inventor： CHEN, Jia-yi
CPC classification number: H04L7/0041 , H03K3/037 , H03K5/22 , H03L7/0816 , H03L7/0818 , H03L7/085 , H03L7/087 , H03L7/0995 , H04L7/0045 , H04L7/0332
Abstract: Certain aspects of the present disclosure provide fully differential phase detectors for use in delay-locked loops, for example. One example phase detecting circuit generally includes a first input for a reference signal; a second input for an input signal to be compared with the reference signal; a set-reset (S-R) latch having a set input, a reset input, a first output, and a second output, and a delay (D) flip-flop having a logic input, a clock input, a reset input, and a logic output. The first input is connected with S-R reset input, the second input is connected with S-R set input, the first S-R output is connected with the D clock input, and the second S-R output is connected with the D reset input. The logic output of the D flip-flop indicates whether the input signal is leading or lagging the reference signal.
Abstract translation: 本公开的某些方面提供例如用于延迟锁定环路的完全差分相位检测器。 一个示例性相位检测电路通常包括用于参考信号的第一输入; 用于与参考信号进行比较的输入信号的第二输入; 具有设定输入，复位输入，第一输出和第二输出的置位复位（SR）锁存器以及具有逻辑输入，时钟输入，复位输入和复位输入的延迟（D）触发器 逻辑输出。 第一个输入与S-R复位输入相连，第二个输入与S-R设定输入相连，第一个S-R输出与D时钟输入相连，第二个S-R输出与D复位输入相连。 D触发器的逻辑输出指示输入信号是引脚还是滞后参考信号。
-
50.发明申请
公开(公告)号：WO2015032338A1
公开(公告)日：2015-03-12
申请号：PCT/CN2014/085938
申请日：2014-09-04
Applicant: MEDIATEK SINGAPORE PTE. LTD. , CHOKE, Tieng Ying , LIN, Jun-Wei
Inventor： CHOKE, Tieng Ying , LIN, Jun-Wei
IPC: H04W88/00
CPC classification number: H04L7/0331 , H04B5/00 , H04B5/0031 , H04B5/0075 , H04L7/0037 , H04L7/0041 , H04L7/0087 , H04L27/0008 , H04L27/02 , H04L27/06 , H04W4/80
Abstract: An envelope extracting apparatus includes: a clock extracting device arranged to extract a clock signal of a receiving modulation signal according to a first biasing voltage; and an edge detecting device arranged to generate a detecting signal to indicate an envelope edge of the receiving modulation signal according to a delayed clock signal of the clock signal and a second biasing voltage; wherein the second biasing voltage or a delay time of the clock signal is adjustable.
Abstract translation: 包络提取装置包括：时钟提取装置，被配置为根据第一偏置电压提取接收调制信号的时钟信号; 以及边缘检测装置，被配置为根据时钟信号的延迟时钟信号和第二偏置电压产生检测信号以指示接收调制信号的包络边缘; 其中所述第二偏置电压或所述时钟信号的延迟时间是可调节的。
-
-
-
-
-
-
-
-
-
Search Results
85
records
(took 0.011 seconds)
