公开(公告)号：WO2006135827A1

公开(公告)日：2006-12-21

申请号：PCT/US2006/022652

申请日：2006-06-08

Applicant: RAMBUS INC. ,  ALON, Elad ,  STOJANOVIC, Vladimir, Marko ,  AMIRKHANY, Amir

Inventor： ALON, Elad ,  STOJANOVIC, Vladimir, Marko ,  AMIRKHANY, Amir

IPC: H04L27/26 ,  G06F17/10

CPC classification number: H04L1/0033

Abstract: A transmitter with data stream transformation circuitry is described. The transmitter has a first driver and a second driver. Each driver has an output for a respective analog signal. A summation circuit combines respective analog signals from the first driver and the second driver. A data selection circuit processes at least two data streams. Each data stream corresponds to a time sequence of digital data symbols. The data selection circuit selectively couples at least one of the data streams to at least one of the drivers during each time interval of a sequence of time intervals, thereby applying a linear transformation to the data streams. A finite state machine controls the data selection circuit during each time interval of the sequence of time intervals.

Abstract translation: 描述了具有数据流转换电路的发射机。 发射机具有第一驱动器和第二驱动器。 每个驱动器都有一个相应模拟信号的输出。 求和电路组合来自第一驱动器和第二驱动器的相应的模拟信号。 数据选择电路处理至少两个数据流。 每个数据流对应于数字数据符号的时间序列。 在时间序列序列的每个时间间隔期间，数据选择电路将至少一个数据流选择性地耦合到至少一个驱动器，从而对数据流进行线性变换。 有限状态机在时间间隔序列的每个时间间隔期间控制数据选择电路。

公开(公告)号：WO2005060193A2

公开(公告)日：2005-06-30

申请号：PCT/US2004/042195

申请日：2004-12-16

Applicant: RAMBUS INC. ,  STOJANOVIC, Vladimir, M. ,  HO, Andrew ,  BESSIOS, Anthony ,  CHEN, Fred, F. ,  ALON, Elad ,  HOROWITZ, Mark, A. ,  GARLEPP, Bruno, W.

Inventor： STOJANOVIC, Vladimir, M. ,  HO, Andrew ,  BESSIOS, Anthony ,  CHEN, Fred, F. ,  ALON, Elad ,  HOROWITZ, Mark, A. ,  GARLEPP, Bruno, W.

IPC: H04L25/49

CPC classification number: H04L25/03057 ,  H04L25/028 ,  H04L25/0292 ,  H04L25/03343 ,  H04L25/061 ,  H04L25/4906

公开(公告)号：WO2007024446A3

公开(公告)日：2008-09-18

申请号：PCT/US2006030411

申请日：2006-08-02

Applicant: RAMBUS INC ,  AMIRKHANY AMIR ,  STOJANOVIC VLADIMIR M ,  ALON ELAD ,  ZERBE JARED L ,  HOROWITZ MARK A

Inventor： AMIRKHANY AMIR ,  STOJANOVIC VLADIMIR M ,  ALON ELAD ,  ZERBE JARED L ,  HOROWITZ MARK A

IPC: G06J1/00 ,  G06F17/14

CPC classification number: G06F17/141 ,  G06J1/005

Abstract: A transform circuit includes a first circuit and a second circuit. The first circuit and the second circuit implement first and second mappings that together generate a pre-defined transform of N digital data symbols. The first circuit maps a set of N digital data symbols from N parallel data streams to N analog data symbols by generating N sets of first weighted sums of the N digital data symbols. Each respective first weighted sum is defined by a respective set of pre-determined first weighting values in a first matrix. The second circuit maps the N analog data symbols to a sequence of N output signals over N time intervals. Each of the N output signals corresponds to a respective second weighted sum of the N analog data symbols. Each respective second weighted sum is defined by a respective set of pre-determined second weighting values in a second matrix.

Abstract translation: 变换电路包括第一电路和第二电路。 第一电路和第二电路实现一起产生N个数字数据符号的预定义变换的第一和第二映射。 第一电路通过产生N个数字数据符号的第一加权和的N组，将来自N个并行数据流的一组N个数字数据符号映射到N个模拟数据符号。 每个相应的第一加权和由第一矩阵中的预定的第一加权值的相应集合来定义。 第二电路在N个时间间隔内将N个模拟数据符号映射到N个输出信号的序列。 N个输出信号中的每一个对应于N个模拟数据符号的相应的第二加权和。 每个相应的第二加权和由第二矩阵中的预定的第二加权值的相应集合来定义。

公开(公告)号：WO2005062469A1

公开(公告)日：2005-07-07

申请号：PCT/US2004/040483

申请日：2004-12-03

Applicant: RAMBUS, INC. ,  HO, Andrew ,  STOJANOVIC, Vladimir ,  CHEN, Fred, F. ,  ALON, Elad ,  HOROWITZ, Mark, A.

Inventor： HO, Andrew ,  STOJANOVIC, Vladimir ,  CHEN, Fred, F. ,  ALON, Elad ,  HOROWITZ, Mark, A.

IPC: H03K19/003

CPC classification number: H04L47/10 ,  H04L5/20 ,  H04L25/0276

Abstract: Described are communication systems that convey differential and common-mode signals over the same differential channel. Noise-tolerant communication schemes use low-amplitude common-mode signals that are easily refected by differential receivers thus allowing for very high differential data rates. Some embodiments employ the common-mode signals to transmit bacchanal signals for adjusting the characteristics of the differential transmitter. Backchannel control signals are effectively conveyed even if the forward channel transmitter is so maladjusted that the received differential data is unrecognizable. Systems in accordance with the above-described embodiments obtain these advantages without additional pins or communications channels, and are compatible with both AC-coupled and DC-coupled communications channels. Data coding schemes and corresponding data recovery circuits eliminate the need for complex, high-speed CDR circuits.

Abstract translation: 描述了通过相同的差分通道传送差分和共模信号的通信系统。 耐噪声通信方案使用易于被差分接收机反射的低幅度共模信号，从而允许非常高的差分数据速率。 一些实施例采用共模信号来传输用于调整差分发射机的特性的机构信号。 即使前向信道发射机被调整不正确，接收到的差分数据是无法识别的，反向信道控制信号也被有效地传送。 根据上述实施例的系统在没有附加引脚或通信信道的情况下获得这些优点，并且与AC耦合和DC耦合通信信道兼容。 数据编码方案和相应的数据恢复电路不需要复杂的高速CDR电路。

公开(公告)号：WO2007024446A2

公开(公告)日：2007-03-01

申请号：PCT/US2006/030411

申请日：2006-08-02

Applicant: RAMBUS INC. ,  AMIRKHANY, Amir ,  STOJANOVIC, Vladimir, M. ,  ALON, Elad ,  ZERBE, Jared, L. ,  HOROWITZ, Mark, A.

Inventor： AMIRKHANY, Amir ,  STOJANOVIC, Vladimir, M. ,  ALON, Elad ,  ZERBE, Jared, L. ,  HOROWITZ, Mark, A.

IPC: G06F17/14

CPC classification number: G06F17/141 ,  G06J1/005

Abstract: A transform circuit includes a first circuit and a second circuit. The first circuit and the second circuit implement first and second mappings that together generate a pre-defined transform of N digital data symbols. The first circuit maps a set of N digital data symbols from N parallel data streams to N analog data symbols by generating N sets of first weighted sums of the N digital data symbols. Each respective first weighted sum is defined by a respective set of pre-determined first weighting values in a first matrix. The second circuit maps the N analog data symbols to a sequence of N output signals over N time intervals. Each of the N output signals corresponds to a respective second weighted sum of the N analog data symbols. Each respective second weighted sum is defined by a respective set of pre-determined second weighting values in a second matrix.

Abstract translation: 变换电路包括第一电路和第二电路。 第一电路和第二电路实现一起产生N个数字数据符号的预定义变换的第一和第二映射。 第一电路通过产生N个数字数据符号的第一加权和的N组，将来自N个并行数据流的一组N个数字数据符号映射到N个模拟数据符号。 每个相应的第一加权和由第一矩阵中的预定的第一加权值的相应集合来定义。 第二电路在N个时间间隔内将N个模拟数据符号映射到N个输出信号的序列。 N个输出信号中的每一个对应于N个模拟数据符号的相应的第二加权和。 每个相应的第二加权和由第二矩阵中的预定的第二加权值的相应集合来定义。