公开(公告)号：WO2023038790A1

公开(公告)日：2023-03-16

申请号：PCT/US2022/041200

申请日：2022-08-23

Applicant: RAMBUS INC.

Inventor： KIM, Joohee ,  LEE, Dongyun ,  WOO, Steven C.

IPC: G06F1/04 ,  G11C7/22 ,  G06F1/08

Abstract: Multiple (e.g., four) memory devices on a module are connected to a common pair of differential data strobe signal conductors. The common pair of differential data strobe conductors are also coupled to a memory controller to time the transmission of data to the multiple memory devices and to time the reception of data from the memory devices. The controller calibrates two or more different data transmission delays relative to its transmission of a write data strobe signal on the common pair of differential data strobe conductors. The controller also calibrates to account for two or more different data reception delays (skew) relative to its reception of a read data strobe signal on the common pair of differential data strobe conductors.

公开(公告)号：WO2022271581A1

公开(公告)日：2022-12-29

申请号：PCT/US2022/034142

申请日：2022-06-20

Applicant: RAMBUS INC.

Inventor： WOO, Steven, C. ,  LEE, Dongyun

IPC: G06F13/16

Abstract: A four-channel memory module includes four independent memory channels and dual channel memory devices. The channels of the dual channel memory are accessed independently. Thus, the four channels for accessing the memory module each access one channel of a first set and a second set of dual channel memory devices on the module. Dual channel data buffer devices are also included on the module. The dual channel data buffer devices also retime data strobe signals for accesses to/from the sets of dual channel memory devices.

公开(公告)号：WO2022187089A1

公开(公告)日：2022-09-09

申请号：PCT/US2022/017883

申请日：2022-02-25

Applicant: RAMBUS INC.

Inventor： BEST, Scott, C. ,  VOGELSANG, Thomas ,  HAMBURG, Michael, Alexander ,  MARSON, Mark, Evan ,  HANDSCHUH, Helena ,  HAMPEL, Craig, E. ,  WRIGHT, Kenneth, Lee

IPC: G06F21/72 ,  G06F21/78 ,  G06F21/79

Abstract: An asymmetric key cryptographic system is used to generate a cryptographic certificate for authenticating a memory module. This certificate is generated based on information, readable by the authenticator (e.g., host system), from at least one device on the memory module that is not read in order to obtain the certificate. For example, the certificate for authenticating a module may be stored in the nonvolatile memory of a serial presence detect device. The certificate itself, however, is based at least in part on information read from at least one other device on the memory module. Examples of this other device include a registering clock driver, DRAM device(s), and/or data buffer device(s). In an embodiment, the information read from a device (e.g., DRAM) may be based on one or more device fmgerprint(s) derived from physical variations that occur naturally, and inevitably, during integrated circuit manufacturing.

公开(公告)号：WO2022086703A1

公开(公告)日：2022-04-28

申请号：PCT/US2021/053590

申请日：2021-10-05

Applicant: RAMBUS INC.

Inventor： KELLAM, Mark D.

IPC: G11C11/34 ,  G11C11/56 ,  G11C16/10 ,  G11C16/12 ,  G11C16/34

Abstract: A flash memory cell of a flash memory device is illuminated with light during programming and/or erasing. The wavelength of the light is selected such that the photons impinging on the flash memory cell have an energy that approaches the barrier height (conduction band offset) of the tunnel insulator. Illuminating the flash memory cell during programming/erase increases the tunneling current through the tunnel insulator by way of the photon assisted tunneling (PAT) effect.

公开(公告)号：WO2021178208A1

公开(公告)日：2021-09-10

申请号：PCT/US2021/019642

申请日：2021-02-25

Applicant: RAMBUS INC.

Inventor： VOGELSANG, THOMAS ,  GOPALAKRISHNAN, Liji

IPC: H01L25/065

Abstract: Power consumption in a three-dimensional stack of integrated-circuit memory dies is reduced through selective enabling/disabling of physical signaling interfaces in those dies in response to early transmission of chip identifier information relative to command execution.

公开(公告)号：WO2020197925A1

公开(公告)日：2020-10-01

申请号：PCT/US2020/023584

申请日：2020-03-19

Applicant: RAMBUS INC.

Inventor： VOGELSANG, Thomas ,  HAMPEL, Craig, E.

IPC: G06F13/14 ,  G06F13/28 ,  G06F13/16 ,  G06F12/02

Abstract: Space in a memory is allocated based on the highest used precision. When the maximum used precision is not being used, the bits required for that particular precision level (e.g., floating point format) are transferred between the processor and the memory while the rest are not. A given floating point number is distributed over non-contiguous addresses. Each portion of the given floating point number is located at the same offset within the access units, groups, and/or memory arrays. This allows a sequencer in the memory device to successively access a precision dependent number of access units, groups, and/or memory arrays without receiving additional requests over the memory channel.

公开(公告)号：WO2020176448A1

公开(公告)日：2020-09-03

申请号：PCT/US2020/019606

申请日：2020-02-25

Applicant: RAMBUS INC.

Inventor： PARTSCH, Torsten

IPC: G06F3/00 ,  G06F3/06 ,  G06F5/00

Abstract: In a memory component having a command/address interface, timing interface and data interface, the command/address interface receives a first command/address value from a control component during a first interval and a second command/address value from the control component during a second interval. The timing interface receives a data strobe from the control component during the first interval and a data clock from the control component during the second interval, the data strobe departing from a parked voltage level to commence toggling at a time corresponding to reception of the first command/address value, and the data clock toggling throughout the second interval regardless of second command/address value reception-time. The data interface samples first write data corresponding to the first command/address value at times indicated by toggling of the data strobe, and samples second write data corresponding to the second command/address value at times indicated by toggling of the data clock.

公开(公告)号：WO2020131528A1

公开(公告)日：2020-06-25

申请号：PCT/US2019/065787

申请日：2019-12-11

Applicant: RAMBUS INC.

Inventor： NIKOUKARY, Shahram ,  CHO, Jonghyun ,  JAI, Anand ,  BATRA, Pradeep ,  LUO, Lei

IPC: G11C11/4076 ,  G11C7/22 ,  G06F13/00

Abstract: A memory controller integrated circuit includes a clock signal generator circuit configured to generate a plurality of strobe signals. The memory controller integrated circuit further includes a memory interface circuit coupled to the clock signal generator circuit, the memory interface circuit configured to transmit the plurality of strobe signals to a memory module, wherein each of the plurality of strobe signals is offset with respect to an adjacent strobe signal, and transmit a plurality of data signals to the memory module, wherein a first subset of the plurality of data signals comprises a first nibble and is phase aligned with a first strobe signal of the plurality of strobe signals, and wherein a second subset of the plurality of data signals comprises a second nibble and is phase aligned with a second strobe signal of the plurality of strobe signals.

公开(公告)号：WO2020117481A1

公开(公告)日：2020-06-11

申请号：PCT/US2019/062568

申请日：2019-11-21

Applicant: RAMBUS INC.

Inventor： WARE, Frederick, A. ,  HAYWOOD, Christopher

IPC: G11C11/4093 ,  G11C11/4096 ,  G11C5/04

Abstract: In a modular memory system, a memory control component, first and second memory sockets and data buffer components are all mounted to the printed circuit board. The first and second memory sockets have electrical contacts to electrically engage counterpart electrical contacts of memory modules to be inserted therein, and each of the data buffer components includes a primary data interface electrically coupled to the memory control component, and first and second secondary data interfaces electrically coupled to subsets of the electrical contacts within the first and second memory sockets, respectively.

公开(公告)号：WO2020036740A1

公开(公告)日：2020-02-20

申请号：PCT/US2019/044491

申请日：2019-07-31

Applicant: RAMBUS INC.

Inventor： CHOUDHARY, Prashant ,  WANG, Nanyan

IPC: H04L25/03 ,  H04B1/16

Abstract: An equalizer includes a first feed-forward stage that provides a measure of low-frequency IS I and a second feed-forward stage that includes a cascade of stages each making an IS I estimate. The IS I estimate from each stage is further equalized by application of the measures of low- frequency IS I from the first feed-forward stage and fed to the next in the cascade of stages. The IS I estimates from the stages thus become progressively more accurate. The number of stages applied to a given signal can be optimized to achieve a suitably low bit-error rate. Power is saved by disabling stages which are not required to meet that goal.