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公开(公告)号：WO2023087161A1
公开(公告)日：2023-05-25
申请号：PCT/CN2021/131070
申请日：2021-11-17
Inventor： WANG, Yali , QU, Feng
Abstract: An antenna is provided. The antenna includes a ground plate; a dielectric layer on the ground plate; and a microstrip feed line and a radiating patch on a side of the dielectric layer away from the ground plate, the radiating patch being coupled to the microstrip feed line and configured to receive a signal from the microstrip feed line. The radiating patch includes a main body having a parallelogram shape with a first notch truncating a corner of the parallelogram shape, at least a portion of the main body truncated by the first notch having an arc-shaped contour line. The radiating patch further includes a first branch structure.
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公开(公告)号：WO2020258282A1
公开(公告)日：2020-12-30
申请号：PCT/CN2019/093830
申请日：2019-06-28
Inventor： LIANG, Kui
IPC: G01T1/20 , H01L27/146
Abstract: A radiation detector having a plurality of pixels is provided. A respective one of the plurality of pixels includes a thin film transistor(TFT) on a base substrate(10); an inter-layer dielectric layer(20) on a side of the thin film transistor(TFT) away from the base substrate(10); a sensing electrode(S) and a bias electrode(B) on a side of the inter-layer dielectric layer(20) away from the base substrate(10), wherein the sensing electrode(S) extends through the inter-layer dielectric layer(20) to electrically connect to the thin film transistor(TFT); a passivation layer(30) on a side of the sensing electrode(S) and the bias electrode(B) away from the inter-layer dielectric layer(20), wherein the passivation layer(30) includes a first portion(31) and a second portion(32); and a radiation detection layer(40) on a side of the passivation layer(30) away from the base substrate(10). The first portion(31) and the second portion(32) form a substantially flat contacting surface(CS).
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公开(公告)号：WO2020258023A1
公开(公告)日：2020-12-30
申请号：PCT/CN2019/092746
申请日：2019-06-25
Inventor： CHENG, Hongfei
IPC: H01L27/12
Abstract: An array substrate having a plurality of subpixels is provided. In a respective one of the plurality of subpixels, the array substrate includes a base substrate; and a thin film transistor on the base substrate. The thin film transistor includes a gate electrode, a source electrode, and a drain electrode. The drain electrode includes a first portion, a second portion, and a third portion connecting the first portion and the second portion. An orthographic projection of the first portion on the base substrate at least partially overlaps with an orthographic projection of a first gate line protrusion of a respective one of the plurality of gate lines on the base substrate. An orthographic projection of the second portion on the base substrate at least partially overlaps with an orthographic projection of a second gate line protrusion of the respective one of the plurality of gate lines on the base substrate.
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公开(公告)号：WO2020151381A1
公开(公告)日：2020-07-30
申请号：PCT/CN2019/123922
申请日：2019-12-09
Inventor： XIAN, Jianbo , LONG, Chunping , LI, Hui , QIAO, Yong
IPC: G09G3/3266 , G09G3/36
Abstract: A driving unit, a gate driving circuit, an array substrate, and a display apparatus. The driving unit includes a first driving sub-circuit (1), a second driving sub-circuit (2), and a driving control circuit (3). The first driving sub-circuit (1) includes a plurality of first switching elements (11), and at least some of the plurality of first switching elements (11) can be configured to output a first signal to a first output terminal (103) of the driving unit in response to a control signal from the driving control circuit (3). The second driving sub-circuit (2) includes one or more second switching elements (21), and at least one of the one or more second switching elements (21) can be configured to output a second signal to a second output terminal (203) of the driving unit in response to the control signal from the driving control circuit (3). The driving control circuit (3) can be configured to output the control signal at a control signal output terminal (301).
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公开(公告)号：WO2023070444A1
公开(公告)日：2023-05-04
申请号：PCT/CN2021/127062
申请日：2021-10-28
Inventor： FENG, Jingwen , MEI, Wenhai , WANG, Haowei
Abstract: A quantum dots material solution is provided. The quantum dots material solution includes a quantum dots material; a ligand chelated to the quantum dots material; a first material capable of generating, upon a first irradiation, a quencher quenching the quantum dots material; a second material capable of at least partially converting the quantum dots material in a plurality of block regions from a first form into a second form. The quantum dots material in the second form has a lower solubility in a developing solution than the quantum dots material in the first form.
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Patent Agency Ranking6.发明申请
公开(公告)号：WO2023023988A1
公开(公告)日：2023-03-02
申请号：PCT/CN2021/114595
申请日：2021-08-25
Inventor： WEI, Xiangye , WANG, Zhiliang
Abstract: A method for generating pseudo-random number is provided. The method includes receiving, by at least one processor, an initial state and a seed; performing, by the at least one processor, at least a cycle of state transfer calculation; and outputting a series of pseudo random numbers. A variable decimal seed is used in at least one step of the at least a cycle of state transfer calculation. The variable decimal seed is calculated in a previous step of the at least a cycle of state transfer calculation.
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公开(公告)号：WO2021077246A1
公开(公告)日：2021-04-29
申请号：PCT/CN2019/112164
申请日：2019-10-21
Inventor： WEI, Xiangye , XIU, Liming , BAI, Yiming , LI, Xin
IPC: H03L7/18
Abstract: A digital clock circuit is provided. The digital clock circuit includes a first sub-circuit comprising a first digitally-controlled oscillator driven by a frequency control word to control a first output frequency synthesized from multiple first pulses, and a first frequency divider to generate a trigger signal having a frequency equal to 1/M of the first output frequency. The digital clock circuit also includes a second sub-circuit comprising a loop of feedback including a frequency detector to compare an input frequency with a feedback frequency, a controller to adjust the frequency control word, a second digitally-controlled oscillator driven by the frequency control word plus a constant to control a second output frequency synthesized from multiple second pulses induced by the trigger signal, and a second frequency divider to set the feedback frequency equal to 1/N of the second output frequency in the loop of feedback.
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公开(公告)号：WO2020192208A1
公开(公告)日：2020-10-01
申请号：PCT/CN2019/127853
申请日：2019-12-24
Inventor： CHENG, Hongfei
IPC: G09G3/3233
Abstract: An array substrate may include a pixel unit. The pixel unit may include a third transistor (T3), a sixth transistor (T6), a light emitting device (F), and a boosting capacitor (Ca). The boosting capacitor (Ca) may include a first electrode (T1) and a second electrode (T2). A control terminal, a first terminal, and a second terminal of the third transistor (T3) may be electrically connected to a first node, a second node, and a third node, respectively. A control terminal, a first terminal and a second terminal of the sixth transistor (T6) may be electrically connected to an emission signal line (EM), a first terminal of the light emitting device (F), and the second node, respectively. The first electrode and the second electrode of the boosting capacitor (Ca) may be electrically connected to a gate line (Gn) and the first node, respectively.
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9.发明申请
公开(公告)号：WO2020119024A1
公开(公告)日：2020-06-18
申请号：PCT/CN2019/087443
申请日：2019-05-17
Inventor： SUN, Tuo
Abstract: A shift register unit having a cascade input terminal, a cascade output terminal and a scan output terminal are disclosed. The shift register unit may include a first shift circuit (12), a second shift circuit (13), an input circuit (11), and a control circuit (14). The input circuit (11) may be configured to provide an input signal from the cascade input terminal to an input terminal of the first shift circuit (12) under control of an input clock terminal. The control circuit (14) may be configured to control connection of an output terminal of the first shift circuit (12) and an input terminal of the second shift circuit (13) based on a signal at a first control terminal.
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公开(公告)号：WO2020113847A1
公开(公告)日：2020-06-11
申请号：PCT/CN2019/078499
申请日：2019-03-18
Inventor： LI, Xinguo , XU, Chen , WU, Xinyin , QIAO, Yong , HAO, Xueguang
IPC: G09G3/3208
Abstract: Disclosed is a shift register for a display panel. The shift register may include an input terminal, an output terminal, an input unit, an output unit, a first control unit, a second control unit, and a first isolation unit. The output unit may be configured to transmit a first level or a second level to an output terminal based on levels of a first node and a second node.
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