公开(公告)号：WO2009083890A1

公开(公告)日：2009-07-09

申请号：PCT/IB2008/055485

申请日：2008-12-22

Applicant: NXP B.V. ,  BERGVELD, Hendrik Johannes ,  WEEKAMP, Johannes Wilhelmus ,  GRUNSVEN, Eric Cornelis Egbertus Van

Inventor： BERGVELD, Hendrik Johannes ,  WEEKAMP, Johannes Wilhelmus ,  GRUNSVEN, Eric Cornelis Egbertus Van

IPC: H05K1/02 ,  H05K1/14

CPC classification number: H05K1/023 ,  H05K1/0231 ,  H05K1/0233 ,  H05K1/145 ,  H05K2201/0999 ,  H05K2201/1003 ,  H05K2201/10515 ,  H05K2201/1053 ,  H05K2201/10636 ,  H05K2201/10727 ,  Y02P70/611

Abstract: A method and apparatus relating to chip-scale packaging is provided. According to an embodiment of the invention electrical solder bump interconnection between an integrated circuit package and a substrate is replaced by the placement and attachment of discrete SMD components between pads on the integrated circuit and substrate. Said substrate being for example a low-temperature co-fired ceramic such as alumina or a PCB such as FR4. Accordingly discrete SMD capacitors, inductors etc can be packaged with the system design goals of minimizing board real-estate, enhancing performance, and cost addressed in a novel manner without requiring substantial development of new processes by manufacturers. The embodiments of the invention minimizing the parasitic series impedance of decoupling capacitor connections for example whilst allowing a small-form-factor System-in-Package to be realized.

Abstract translation: 提供了与芯片级封装相关的方法和装置。 根据本发明的实施例，集成电路封装和衬底之间的电焊料凸块互连由集成电路和衬底上的衬垫之间的离散SMD组件的放置和附接所代替。 所述基材例如是低温共烧陶瓷如氧化铝或PCB如FR4。 因此，分立式SMD电容器，电感器等可以将系统设计目标最小化，从而最大限度地减少电路板的不动产，提高性能，并以新颖的方式解决成本，而无需制造商大量开发新工艺。 本发明的实施例使去耦电容器连接的寄生串联阻抗最小化，例如同时允许实现小尺寸系统级封装。