公开(公告)号：WO2013014974A1

公开(公告)日：2013-01-31

申请号：PCT/JP2012/057246

申请日：2012-03-14

Applicant: Kabushiki Kaisha Toshiba ,  HORISAKI, Koji ,  HIDA, Toshikatsu ,  KANNO, Shinichi ,  TORII, Osamu

Inventor： HORISAKI, Koji ,  HIDA, Toshikatsu ,  KANNO, Shinichi ,  TORII, Osamu

IPC: G06F12/16 ,  G11C29/42

CPC classification number: G06F11/1044 ,  G06F11/1048 ,  H03M13/1575

Abstract: According to an embodiment, a memory interface that includes n number of channels and writes data subjected to an error correction encoding process having capable of correcting t symbols, n number of first error correction decoding units that perform an error correction decoding process of correcting s (s

Abstract translation: 根据一个实施例，一种存储器接口，其包括n个通道并且写入经过能够校正t个符号的纠错编码处理的数据，n个第一纠错解码单元，其执行校正s（ s