公开(公告)号：WO2009155474A2

公开(公告)日：2009-12-23

申请号：PCT/US2009/047884

申请日：2009-06-19

Applicant: TEXAS INSTRUMENTS INCORPORATED ,  MIKAN, Donald, George ,  MAIR, Hugh ,  HOUSTON, Theodore, W. ,  CLINTON, Michael, Patrick

Inventor： MIKAN, Donald, George ,  MAIR, Hugh ,  HOUSTON, Theodore, W. ,  CLINTON, Michael, Patrick

IPC: G11C5/14 ,  G11C7/22 ,  G11C7/12 ,  G11C8/08

CPC classification number: G11C7/02 ,  G11C11/413

Abstract: A memory array is provided having a memory cell (40) coupled to a read word line and a write word line of the memory array and peripheral circuits for reading and writing to the memory cell. The memory cell comprises a storage element (42) for storing a logical state of the memory cell powered at a reduced voltage during at least one functional operation and a write access circuit configured to connect the storage element to at least a first write bit line (44) in the memory array in response to a write signal on the write word line for writing the logical state to the memory cell. The memory cell further comprises a read access circuit including an input node connected to the storage element and an output node connected to a read bit line of the memory array. The read access circuit is enabled and configured to read the logic state of the storage element in response to a read signal on the read word line. The reduced voltage is a voltage that is reduced relative to a peripheral operating voltage of at least one peripheral circuit associated with reading and/or writing of the memory cell.

Abstract translation: 提供了存储器阵列，其具有耦合到读取字线和存储器阵列的写入字线的存储器单元（40）和用于读取和写入存储器单元的外围电路。 存储单元包括用于存储在至少一个功能操作期间以降低的电压供电的存储单元的逻辑状态的存储元件（42），以及被配置为将存储元件连接到至少第一写入位线的写入存取电路 44）在存储器阵列中响应写入字线上的写入信号而将逻辑状态写入存储器单元。 存储单元还包括读取存取电路，其包括连接到存储元件的输入节点和连接到存储器阵列的读取位线的输出节点。 读取访问电路被启用并被配置为响应于读取的字线上的读取信号来读取存储元件的逻辑状态。 降低的电压是相对于与存储器单元的读取和/或写入相关联的至少一个外围电路的外围工作电压而降低的电压。

公开(公告)号：WO2008073745A2

公开(公告)日：2008-06-19

申请号：PCT/US2007/086265

申请日：2007-12-03

Applicant: TEXAS INSTRUMENTS INCORPORATED ,  HOUSTON, Theodore, W. ,  CLINTON, Michael, P. ,  PITTS, Robert, L.

Inventor： HOUSTON, Theodore, W. ,  CLINTON, Michael, P. ,  PITTS, Robert, L.

IPC: G05F1/10

CPC classification number: G05F3/205

Abstract: The invention (100) provides a tunable voltage controller for use with a sub-circuit (105). In one embodiment, the tunable voltage controller (115) includes a diode-connected MOS transistor contained in a doped well of a substrate and configured to provide a voltage for the sub-circuit. Additionally, the tunable voltage controller also includes a biasing unit (120) configured to adjust the voltage by selectively connecting the doped well to one of a plurality of voltage sources or to a variable voltage source.

Abstract translation: 本发明（100）提供了一种与子电路（105）一起使用的可调电压控制器。 在一个实施例中，可调谐电压控制器（115）包括二极管连接的MOS晶体管，其包含在衬底的掺杂阱中并且被配置为为子电路提供电压。 此外，可调谐电压控制器还包括偏置单元（120），其被配置为通过将掺杂阱选择性地连接到多个电压源中的一个或可变电压源来调节电压。

公开(公告)号：WO2008073745A3

公开(公告)日：2009-01-08

申请号：PCT/US2007086265

申请日：2007-12-03

Applicant: TEXAS INSTRUMENTS INC ,  HOUSTON THEODORE W ,  CLINTON MICHAEL P ,  PITTS ROBERT L

Inventor： HOUSTON THEODORE W ,  CLINTON MICHAEL P ,  PITTS ROBERT L

IPC: H03K3/01 ,  G11C5/14

CPC classification number: G05F3/205

Abstract: The invention (100) provides a tunable voltage controller for use with a sub-circuit (105). In one embodiment, the tunable voltage controller (115) includes a diode-connected MOS transistor contained in a doped well of a substrate and configured to provide a voltage for the sub-circuit. Additionally, the tunable voltage controller also includes a biasing unit (120) configured to adjust the voltage by selectively connecting the doped well to one of a plurality of voltage sources or to a variable voltage source.

Abstract translation: 本发明（100）提供了一种与子电路（105）一起使用的可调电压控制器。 在一个实施例中，可调谐电压控制器（115）包括二极管连接的MOS晶体管，其包含在衬底的掺杂阱中并且被配置为为子电路提供电压。 此外，可调谐电压控制器还包括偏置单元（120），其被配置为通过将掺杂阱选择性地连接到多个电压源中的一个或可变电压源来调节电压。

公开(公告)号：WO2006009849A3

公开(公告)日：2006-06-08

申请号：PCT/US2005021470

申请日：2005-06-17

Applicant: TEXAS INSTRUMENTS INC ,  SADRA KAYVAN ,  HOUSTON THEODORE W

Inventor： SADRA KAYVAN ,  HOUSTON THEODORE W

IPC: G11C5/06 ,  H01L27/11

CPC classification number: H01L27/1104

Abstract: A method of placing a cell in an array is disclosed. The method includes placing the cell a plurality of times (600, 602, 604) in a first array. The cell is also placed a plurality of times (606, 608, 610) in a second array. The second array is placed adjacent and offset from the first array by an offset distance (O 2 ).

Abstract translation: 公开了将阵列放置在阵列中的方法。 该方法包括将单元多次（600,602,604）放置在第一阵列中。 单元还在第二阵列中放置多次（606,608,610）。 第二阵列被放置在与第一阵列相邻并偏移一个偏移距离（O 2 2 N）的位置。

公开(公告)号：WO2009058991A1

公开(公告)日：2009-05-07

申请号：PCT/US2008/081771

申请日：2008-10-30

Applicant: TEXAS INSTRUMENTS INCORPORATED ,  HOUSTON, Theodore, W. ,  MARSHALL, Andrew

Inventor： HOUSTON, Theodore, W. ,  MARSHALL, Andrew

IPC: G11C5/14 ,  G11C7/10 ,  G11C8/14 ,  G11C7/18

CPC classification number: G11C5/14 ,  G11C8/08 ,  G11C11/413

Abstract: An integrated circuit (IC) (200) includes at least one memory array having a plurality of memory cells (240) arranged in a plurality of rows and columns, the array also having a plurality of word lines for accessing rows of cells and a plurality bit lines for accessing columns of cells. A voltage differential generating circuit (230) is operable to provide a differential wordline voltage (VWL) relative to an array supply voltage, wherein the differential is a function of the array supply voltage.

Abstract translation: 集成电路（IC）（200）包括至少一个存储器阵列，其具有以多个行和列排列的多个存储单元（240），该阵列还具有用于访问单元行的多个字线和多个 用于访问单元格列的位线。 电压差分发生电路（230）可操作以提供相对于阵列电源电压的差分字线电压（VWL），其中差分是阵列电源电压的函数。

公开(公告)号：WO2007041029A3

公开(公告)日：2009-04-16

申请号：PCT/US2006037021

申请日：2006-09-22

Applicant: TEXAS INSTRUMENTS INC ,  YANG SHYH-HORNG ,  SADRA KAYVAN ,  HOUSTON THEODORE W

Inventor： YANG SHYH-HORNG ,  SADRA KAYVAN ,  HOUSTON THEODORE W

IPC: H01L21/8238

CPC classification number: H01L27/1104 ,  H01L21/26586 ,  H01L27/0207 ,  H01L27/11 ,  H01L29/1045 ,  H01L29/66659

Abstract: A method of fabricating an SRAM cell with reduced leakage is disclosed. The method comprises fabricating asymmetrical transistors in the SRAM cell. The transistors are asymmetrical in a manner that reduces the drain leakage current of the transistors. The fabrication of asymmetrical pass transistors comprises forming a dielectric region (516) on a surface of a substrate having a first conductivity type. A gate region (500) having a length and a width is formed on the dielectric region. Source and drain extension regions (506, 510) having a second conductivity type are formed in the substrate on opposite sides of the gate region. A first pocket impurity region (508) having a first concentration and the first conductivity type is formed adjacent the source. A second pocket impurity region having a second concentration and the first conductivity type may be formed adjacent the drain. If formed, the second concentration is smaller than the first concentration, reducing the gate induced drain leakage current.

Abstract translation: 公开了一种制造具有减少泄漏的SRAM单元的方法。 该方法包括在SRAM单元中制造不对称晶体管。 晶体管以不减小晶体管的漏极漏电流的方式是不对称的。 不对称传输晶体管的制造包括在具有第一导电类型的衬底的表面上形成电介质区域（516）。 在电介质区域上形成具有长度和宽度的栅极区域（500）。 具有第二导电类型的源极和漏极延伸区域（506,510）形成在栅极区域的相对侧上的衬底中。 在源附近形成具有第一浓度和第一导电类型的第一杂质杂质区（508）。 可以在漏极附近形成具有第二浓度和第一导电类型的第二袋杂质区域。 如果形成，则第二浓度小于第一浓度，减小了栅极引起的漏极漏电流。

公开(公告)号：WO2007021668A3

公开(公告)日：2007-02-22

申请号：PCT/US2006/030840

申请日：2006-08-09

Applicant: TEXAS INSTRUMENTS INCORPORATED ,  HOUSTON, Theodore, W.

Inventor： HOUSTON, Theodore, W.

IPC: G11C11/41 ,  G11C11/412 ,  H01L27/11 ,  H01L21/8244

Abstract: The invention provides circuitry for writing to and reading from an SRAM cell core (105), an SRAM cell (100), and an SRAM device. In one aspect, the circuitry includes a write circuit coupled to the SRAM cell core that includes at least one write transistor (150). The circuitry also includes a read circuit coupled to the SRAM cell core that includes at least one read transistor (185) having a gate signal in common with the gate signal of the write transistor. The read transistor and the write transistor share a common gate signal, and each have an electrical characteristic, for which the electrical characteristic of the read transistor differs from that of the write transistor.

公开(公告)号：WO2007021668A2

公开(公告)日：2007-02-22

申请号：PCT/US2006030840

申请日：2006-08-09

Applicant: TEXAS INSTRUMENTS INC ,  HOUSTON THEODORE W

Inventor： HOUSTON THEODORE W

IPC: G11C11/00

CPC classification number: G11C11/413 ,  G11C7/1051 ,  G11C7/1069 ,  G11C7/1078 ,  G11C7/1096 ,  G11C11/412

Abstract: The invention provides circuitry for writing to and reading from an SRAM cell core (105), an SRAM cell (100), and an SRAM device. In one aspect, the circuitry includes a write circuit coupled to the SRAM cell core that includes at least one write transistor (150). The circuitry also includes a read circuit coupled to the SRAM cell core that includes at least one read transistor (185) having a gate signal in common with the gate signal of the write transistor. The read transistor and the write transistor share a common gate signal, and each have an electrical characteristic, for which the electrical characteristic of the read transistor differs from that of the write transistor.

Abstract translation: 本发明提供了用于向SRAM单元核心（105），SRAM单元（100）和SRAM器件进行写入和读取的电路。 在一个方面，电路包括耦合到SRAM单元芯的写入电路，其包括至少一个写入晶体管（150）。 电路还包括耦合到SRAM单元芯的读取电路，其包括至少一个具有与写入晶体管的栅极信号共同的栅极信号的读取晶体管（185）。 读取晶体管和写入晶体管共享公共栅极信号，并且每个具有电特性，读取晶体管的电特性与写入晶体管的电特性不同。

公开(公告)号：WO2009155474A3

公开(公告)日：2010-03-25

申请号：PCT/US2009047884

申请日：2009-06-19

Applicant: TEXAS INSTRUMENTS INC ,  MIKAN DONALD GEORGE ,  MAIR HUGH ,  HOUSTON THEODORE W ,  CLINTON MICHAEL PATRICK

Inventor： MIKAN DONALD GEORGE ,  MAIR HUGH ,  HOUSTON THEODORE W ,  CLINTON MICHAEL PATRICK

IPC: G11C5/14 ,  G11C7/12 ,  G11C7/22 ,  G11C8/08

CPC classification number: G11C7/02 ,  G11C11/413

Abstract: A memory array is provided having a memory cell (40) coupled to a read word line and a write word line of the memory array and peripheral circuits for reading and writing to the memory cell. The memory cell comprises a storage element (42) for storing a logical state of the memory cell powered at a reduced voltage during at least one functional operation and a write access circuit configured to connect the storage element to at least a first write bit line (44) in the memory array in response to a write signal on the write word line for writing the logical state to the memory cell. The memory cell further comprises a read access circuit including an input node connected to the storage element and an output node connected to a read bit line of the memory array. The read access circuit is enabled and configured to read the logic state of the storage element in response to a read signal on the read word line. The reduced voltage is a voltage that is reduced relative to a peripheral operating voltage of at least one peripheral circuit associated with reading and/or writing of the memory cell.

Abstract translation: 提供了存储器阵列，其具有耦合到读取字线和存储器阵列的写入字线的存储器单元（40）和用于读取和写入存储器单元的外围电路。 存储单元包括用于存储在至少一个功能操作期间以降低的电压供电的存储单元的逻辑状态的存储元件（42），以及被配置为将存储元件连接到至少第一写位线的写存取电路 44）在存储器阵列中响应写入字线上的写入信号而将逻辑状态写入存储器单元。 存储单元还包括读取存取电路，其包括连接到存储元件的输入节点和连接到存储器阵列的读取位线的输出节点。 读取访问电路被启用并被配置为响应于读取的字线上的读取信号来读取存储元件的逻辑状态。 降低的电压是相对于与存储器单元的读取和/或写入相关联的至少一个外围电路的外围工作电压而降低的电压。

公开(公告)号：WO2007041029A2

公开(公告)日：2007-04-12

申请号：PCT/US2006/037021

申请日：2006-09-22

Applicant: TEXAS INSTRUMENTS INCORPORATED ,  YANG, Shyh-Horng ,  SADRA, Kayvan ,  HOUSTON, Theodore, W.

Inventor： YANG, Shyh-Horng ,  SADRA, Kayvan ,  HOUSTON, Theodore, W.

IPC: H01L21/8238

CPC classification number: H01L27/1104 ,  H01L21/26586 ,  H01L27/0207 ,  H01L27/11 ,  H01L29/1045 ,  H01L29/66659

Abstract: A method of fabricating an SRAM cell with reduced leakage is disclosed. The method comprises fabricating asymmetrical transistors in the SRAM cell. The transistors are asymmetrical in a manner that reduces the drain leakage current of the transistors. The fabrication of asymmetrical pass transistors comprises forming a dielectric region (516) on a surface of a substrate having a first conductivity type. A gate region (500) having a length and a width is formed on the dielectric region. Source and drain extension regions (506, 510) having a second conductivity type are formed in the substrate on opposite sides of the gate region. A first pocket impurity region (508) having a first concentration and the first conductivity type is formed adjacent the source. A second pocket impurity region having a second concentration and the first conductivity type may be formed adjacent the drain. If formed, the second concentration is smaller than the first concentration, reducing the gate induced drain leakage current.

Abstract translation: 公开了一种制造具有减少泄漏的SRAM单元的方法。 该方法包括在SRAM单元中制造不对称晶体管。 晶体管以不减小晶体管的漏极漏电流的方式是不对称的。 不对称传输晶体管的制造包括在具有第一导电类型的衬底的表面上形成电介质区域（516）。 在电介质区域上形成具有长度和宽度的栅极区域（500）。 具有第二导电类型的源极和漏极延伸区域（506,510）形成在栅极区域的相对侧上的衬底中。 在源附近形成具有第一浓度和第一导电类型的第一杂质杂质区（508）。 可以在漏极附近形成具有第二浓度和第一导电类型的第二袋杂质区域。 如果形成，则第二浓度小于第一浓度，减小了栅极引起的漏极漏电流。