A DIGITAL SAMPLE CLOCK GENERATOR, A VIBRATION GYROSCOPE CIRCUITRY COMPRISING SUCH DIGITAL SAMPLE CLOCK GENERATOR, AN ASSOCIATED APPARATUS, AN ASSOCIATED SEMICONDUCTOR DEVICE AND ASSOCIATED METHODS
    1.
    发明申请
    A DIGITAL SAMPLE CLOCK GENERATOR, A VIBRATION GYROSCOPE CIRCUITRY COMPRISING SUCH DIGITAL SAMPLE CLOCK GENERATOR, AN ASSOCIATED APPARATUS, AN ASSOCIATED SEMICONDUCTOR DEVICE AND ASSOCIATED METHODS 审中-公开
    数字样本时钟发生器,包含这样的数字样本时钟发生器的振动陀螺仪电路,相关设备,相关的半导体器件及相关方法

    公开(公告)号:WO2014006437A1

    公开(公告)日:2014-01-09

    申请号:PCT/IB2012/001449

    申请日:2012-07-04

    Abstract: A digital sample clock generator (SCG) for generating a sample clock signal (SCLK) from an input signal (FD) derived from a drive measurement voltage signal (DMV) of a vibrating MEMS gyroscope (VMEMS) is described. The sample clock generator (SCG) has an oscillator (HFOSC) arranged to generate a master clock (MOSC) with a master clock period, a synchronization unit (SYN) arranged to detect a start of an input signal period (FR_PER) of the input signal (FD) and to, upon detecting the start, generate a synchronization pulse (FD_OSC) in synchronization with the master clock (MOSC), ), a counter unit (OSCCNTR) arrange to count master clock periods between subsequent synchronization pulses to obtain the number of master clock periods between subsequent synchronization pulses as a number count, a multiplier (MULT) arranged to multiply the number count with a pre-determined phase shift fraction (PhPerc) to obtain a number of trim periods, and a delay unit (DLY) arranged to generate the sample clock signal (SLCK) with a clock signal period (SCLK_PER) corresponding to the number count (CNT) and with a delay relative to the synchronization pulse corresponding to the number of trim periods (TRM). A drive-mode vibration gyroscope circuitry (VDCIRC) and a sense-mode vibration gyroscope circuitry (VSCIRC) are also described.

    Abstract translation: 描述了用于从由振动MEMS陀螺仪(VMEMS)的驱动测量电压信号(DMV)导出的输入信号(FD)产生采样时钟信号(SCLK)的数字采样时钟发生器(SCG)。 采样时钟发生器(SCG)具有被配置为产生具有主时钟周期的主时钟(MOSC)的振荡器(HFOSC),被配置为检测输入的输入信号周期(FR_PER)的开始的同步单元(SYN) 信号(FD),并且在检测到开始时,与主时钟(MOSC)同步地生成同步脉冲(FD_OSC)),计数单元(OSCCNTR),其配置为对后续同步脉冲之间的主时钟周期进行计数,以获得 在后续同步脉冲之间作为数字计数的主时钟周期数;乘法器(MULT),被布置为将数量乘以预定相移分数(PhPerc)以获得修剪周期数;以及延迟单元(DLY ),其被布置成以对应于数量计数(CNT)的时钟信号周期(SCLK_PER)并且相对于与修剪周期数(TRM)相对应的同步脉冲具有延迟来生成采样时钟信号(SLCK)。 还描述了驱动模式振动陀螺仪电路(VDCIRC)和感测模式振动陀螺仪电路(VSCIRC)。

    METHOD FOR RECOVERING CATALYST METAL FROM WASTE OF TEREPHTHALIC ACID PRODUCTION
    2.
    发明申请
    METHOD FOR RECOVERING CATALYST METAL FROM WASTE OF TEREPHTHALIC ACID PRODUCTION 审中-公开
    从过硫酸生产废物中回收催化剂金属的方法

    公开(公告)号:WO2005049873A1

    公开(公告)日:2005-06-02

    申请号:PCT/KR2004/002978

    申请日:2004-11-17

    Abstract: A method for rapidly and environmentally-friendly recovering valuable catalyst metal such as Co, Mn or so on from waste of terephthalic acid production is disclosed. The method comprises the steps of: adjusting pH of the waste of terephthalic acid production to 2.5 to 7; adding NaHCO3 slurry, which is prepared by mixing NaHCO3 and water, into a precipitation reactor, into which the waste of terephthalic acid production is added; heating a mixture of the waste of terephthalic acid production and NaHCO3 slurry; and separating a metal precipitate from the reaction mixture.

    Abstract translation: 公开了一种从对苯二甲酸生产废弃物中迅速回收有价值的催化剂金属如Co,Mn等的方法。 该方法包括以下步骤:将对苯二甲酸生产废物的pH调节至2.5至7; 将通过将NaHCO 3和水混合制备的NaHCO 3浆料加入到其中加入对苯二甲酸生产废料的沉淀反应器中; 加热对苯二甲酸生产废水和NaHCO 3浆料的混合物; 并从反应混合物中分离金属沉淀物。

    CAPACITANCE-TO-VOLTAGE INTERFACE CIRCUIT, AND RELATED OPERATING METHODS

    公开(公告)号:WO2010088041A3

    公开(公告)日:2010-08-05

    申请号:PCT/US2010/020851

    申请日:2010-01-13

    Abstract: A capacitance-to-voltage interface circuit (400) is utilized to obtain a voltage corresponding to a detected capacitance differential, which may be associated with the operation of a capacitive sensing cell (402). The interface circuit (400) includes a capacitive sensing cell (402), an operational amplifier (408) adapted for selective coupling to the capacitive sensing cell (402), a feedback capacitor (412, 414) for the operational amplifier (408), a load capacitor (416, 418) for the operational amplifier (408), and a switching architecture (108) associated with the capacitive sensing cell (402), the operational amplifier (408), the feedback capacitor (412, 414), and the load capacitor (416, 418). During use, the switching architecture (108) reconfigures the capacitance-to-voltage interface circuit (400) for operation in a plurality of different phases. The different operational phases enable the single operational amplifier (408) to be used for both capacitance-to-voltage conversion and voltage amplification.

    CAPACITANCE-TO-VOLTAGE INTERFACE CIRCUIT, AND RELATED OPERATING METHODS
    4.
    发明申请
    CAPACITANCE-TO-VOLTAGE INTERFACE CIRCUIT, AND RELATED OPERATING METHODS 审中-公开
    电容到电压接口电路及相关的操作方法

    公开(公告)号:WO2010088041A2

    公开(公告)日:2010-08-05

    申请号:PCT/US2010020851

    申请日:2010-01-13

    CPC classification number: G01R27/2605 G01D5/24 G01P15/125

    Abstract: A capacitance-to-voltage interface circuit (400) is utilized to obtain a voltage corresponding to a detected capacitance differential, which may be associated with the operation of a capacitive sensing cell (402). The interface circuit (400) includes a capacitive sensing cell (402), an operational amplifier (408) adapted for selective coupling to the capacitive sensing cell (402), a feedback capacitor (412, 414) for the operational amplifier (408), a load capacitor (416, 418) for the operational amplifier (408), and a switching architecture (108) associated with the capacitive sensing cell (402), the operational amplifier (408), the feedback capacitor (412, 414), and the load capacitor (416, 418). During use, the switching architecture (108) reconfigures the capacitance-to-voltage interface circuit (400) for operation in a plurality of different phases. The different operational phases enable the single operational amplifier (408) to be used for both capacitance-to-voltage conversion and voltage amplification.

    Abstract translation: 利用电容 - 电压接口电路(400)来获得与可以与电容式感测单元(402)的操作相关联的检测到的电容差分相对应的电压。 接口电路(400)包括电容性感测单元(402),适于选择性耦合到电容性感测单元(402)的运算放大器(408),用于运算放大器(408)的反馈电容器(412,414) 用于运算放大器(408)的负载电容器(416,418),以及与电容性感测单元(402),运算放大器(408),反馈电容器(412,414)相关联的开关架构(108) 负载电容器(416,418)。 在使用期间,开关架构(108)重新配置电容 - 电压接口电路(400)以用于在多个不同阶段中操作。 不同的操作阶段使单个运算放大器(408)能够用于电容 - 电压转换和电压放大。

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