公开(公告)号：WO2007079098A3

公开(公告)日：2007-09-13

申请号：PCT/US2006049330

申请日：2006-12-27

Applicant: SRIDHARAN KARTIK M

Inventor： SRIDHARAN KARTIK M

IPC: H03L7/16

CPC classification number: H03L7/18 ,  G06F1/022 ,  G06F7/602 ,  H03K21/00

Abstract: A digital frequency synthesizer can be implemented with single source design, a multiplexer design, a fractional divider design, or a frequency multiplier and frequency divider design. Implementations can utilize a controller dithering circuit or a delta-sigma modulator. The frequency synthesizer can be implemented in a CMOS structure and can utilize a clean up phase locked loop (PLL).

Abstract translation: 数字频率合成器可以通过单一信号源设计，多路复用器设计，分数分频器设计或倍频器和分频器设计实现。 实现可以利用控制器抖动电路或delta-sigma调制器。 频率合成器可以用CMOS结构实现，并可以使用清理锁相环（PLL）。

公开(公告)号：WO2006091826A3

公开(公告)日：2006-12-21

申请号：PCT/US2006006619

申请日：2006-02-23

Applicant: MULTIGIG INC ,  WOOD JOHN

Inventor： WOOD JOHN

IPC: H03K21/00 ,  H03L7/18

CPC classification number: H03K21/00

Abstract: A system and method for dividing a clock in a way that achieves low phase noise. In one embodiment, a multi-phase oscillator (20) such as a rotary traveling wave oscillator operates a state machine (26) which determines times at which a transition coupled phase signal of the multi-phase oscillator should be suppressed. Suppression of the transition is performed by a transition structure that holds the phase signal at a high or low so that the transition does not occur at the output. Fewer transitions in the ph signal create a divided clock. In another embodiment, a decoder (24) determines times for suppressing transitions in a true and complement clock and a polarity flip-flop determines the correct polarity for suppressing edges on both clocks. In yet another embodiment, a multiplexer is used to selectively pass either a true or complement clock to an output load.

Abstract translation: 一种以实现低相位噪声的方式分频时钟的系统和方法。 在一个实施例中，诸如旋转行波振荡器的多相位振荡器（20）操作状态机（26），其确定应该抑制多相振荡器的转换耦合相位信号的时间。 通过将相位信号保持在高或低的过渡结构来执行转换的抑制，使得在输出处不发生转换。 Ph信号中更少的转换创建一个分频时钟。 在另一个实施例中，解码器（24）确定用于抑制真和补码时钟中的转换的时间，并且极性触发器确定用于抑制两个时钟上的边沿的正确极性。 在另一个实施例中，多路复用器用于选择性地将真或补时钟传递给输出负载。

公开(公告)号：WO1988000775A1

公开(公告)日：1988-01-28

申请号：PCT/GB1987000487

申请日：1987-07-10

Applicant: HUGHES MICROELECTRONICS LIMITED ,  WARNER, David, John

Inventor： HUGHES MICROELECTRONICS LIMITED

IPC: H03K23/54

CPC classification number: H03K21/403 ,  H03K21/00 ,  H03K23/542

Abstract: An electronic counter such as for use in the odometer of a motor vehicle is provided comprising an array (10) of m rows and n columns of single flip-flop data latches and a central shifting unit (CSU) (14). The CSU (14) comprises a row of n data latches arranged to read data from and write data to each of the m rows of data latches of the array (10). In operation, the CSU (14) reads data from a row of data latches of the array, performs a shift operation on the data and an invert operation on one of n data latches of the CSU (14) and returns the data so operated on to the row of data latches in the array (10). By these steps, a counting operation in Johnson code is performed on the data. This invention uses less chip area than known counters.

公开(公告)号：WO2016011873A1

公开(公告)日：2016-01-28

申请号：PCT/CN2015/082478

申请日：2015-06-26

Applicant: 马恒达

Inventor： 马恒达

IPC: H04R1/10

CPC classification number: H04R5/04 ,  H03K21/00 ,  H03L7/18 ,  H04R1/10 ,  H04R1/1091 ,  H04R1/34 ,  H04R1/40 ,  H04R3/12 ,  H04R3/14 ,  H04R5/02 ,  H04R5/033 ,  H04S5/02

Abstract: 本实用新型公开一种耳机，其包括左听筒、右听筒及音源输入端。左听筒内设有主左喇叭及次左喇叭，右听筒内设有主右喇叭及次右喇叭。音源输入端包括左声道音频输入端及右声道音频输入端。左声道音频输入端通过第三分频器与次右喇叭电性连接，右声道音频输入端通过第四分频器与次左喇叭电性连接。所述第三分频器用于将左声道音频输入端输入的音频信号经过分频处理后传送到次右喇叭，所述第四分频器用于将右声道音频输入端输入的音频信号经过分频处理后传送到次左喇叭。本实用新型提供的耳机，能使用者能体验到前所未有的真实、自然环境听音感受。

公开(公告)号：WO2012042044A8

公开(公告)日：2013-05-02

申请号：PCT/EP2011067188

申请日：2011-09-30

Applicant: ST ERICSSON SA ,  HESEN LEONARDUS ,  MATEMAN PAUL ,  FRAMBACH JOHANNES PETRUS ANTONIUS

Inventor： HESEN LEONARDUS ,  MATEMAN PAUL ,  FRAMBACH JOHANNES PETRUS ANTONIUS

IPC: C07F7/08 ,  H03K21/02

CPC classification number: H03K21/00 ,  H03K21/026 ,  H03K21/12

Abstract: High-speed RF differential, Quadrature, divide-by-2 clock divider designs are based on inverters and clocking circuits connected in a serial ring formation. In one embodiment, only NMOS transistors are used in the inverters, and only PMOS transistors are used in the clocking circuits. This structure uses only 12 transistors. The input can be coupled directly to a VCO output, and provides minimum loading, as each VCO output is connected to only two transistors. Another embodiment comprises clocked inverter stages connected in a serial ring configuration with inverters between stages. The RF clock (or VCO signal) is used at the outer side of the inverters for speed improvement. In both circuits, positive and negative clock inputs are connected alternately at each stage of the ring.

Abstract translation: 高速RF差分，正交，2分频时钟分频器设计基于以串联环形形式连接的逆变器和时钟电路。 在一个实施例中，在反相器中仅使用NMOS晶体管，并且在时钟电路中仅使用PMOS晶体管。 该结构仅使用12个晶体管。 由于每个VCO输出仅连接到两个晶体管，输入可以直接耦合到VCO输出，并提供最小的负载。 另一个实施例包括以串联环形连接的时钟反相级，在级之间具有反相器。 逆变器外侧使用RF时钟（或VCO信号）进行速度改进。 在两个电路中，正和负时钟输入在环的每个阶段交替连接。

公开(公告)号：WO2011008999A1

公开(公告)日：2011-01-20

申请号：PCT/US2010/042191

申请日：2010-07-15

Applicant: QUALCOMM INCORPORATED ,  QIAO, Dongjiang ,  BOSSU, Frederic

Inventor： QIAO, Dongjiang ,  BOSSU, Frederic

IPC: H03K21/00 ,  H03K23/40 ,  H03L7/18

CPC classification number: H03K23/40 ,  H03K21/00

Abstract: A method for dividing the frequency of a signal using a configurable dividing ratio is disclosed. An input signal with a first frequency is received at clocked switches in a frequency divider with a configurable dividing ratio. Non-clocked switches inside the frequency divider are operated to select one of multiple dividing ratios. An output signal is output with a second frequency that is the first frequency divided by the selected dividing ratio.

Abstract translation: 公开了一种使用可配置分频比对信号频率进行分频的方法。 具有第一频率的输入信号在具有可配置分频比的分频器中的时钟开关处被接收。 操作分频器内的非时钟开关可以选择多个分频比之一。 输出信号以第一频率除以选择的分频比的第二频率输出。

公开(公告)号：WO2016065771A1

公开(公告)日：2016-05-06

申请号：PCT/CN2015/072594

申请日：2015-02-09

Applicant: 深圳市中兴微电子技术有限公司

Inventor： 殷俊杰

IPC: H04L12/08

CPC classification number: H03K21/12 ,  G06F13/22 ,  H03K21/00 ,  H04L12/08 ,  H04L49/00

Abstract: 一种计数器，包括：计算模块（100）和N个计数模块（101），每个计数模块中包括多个对应不同计数条目的计数空间，同一计数条目在不同计数模块中计数空间的地址相同；其中，所述计数模块，用于响应一个计数申请源的计数申请，为计算模块提供用于计算的值；所述计算模块，用于读取同一计数条目在不同计数模块的值，将读取到的值进行累计计算，得到所述计数条目的总计数值；所述N为不小于1的整数。还同时公开了一种计数方法。

公开(公告)号：WO2014006437A1

公开(公告)日：2014-01-09

申请号：PCT/IB2012/001449

申请日：2012-07-04

Applicant: FREESCALE SEMICONDUCTOR, INC. ,  BEAULATON, Hugues ,  JO, Sung-Jin

Inventor： BEAULATON, Hugues ,  JO, Sung-Jin

IPC: H03K3/78 ,  G01C19/56 ,  G06F1/04

CPC classification number: G06F1/04 ,  G01C19/5776 ,  G01D5/14 ,  G01D5/243 ,  H03K3/78 ,  H03K21/00

Abstract: A digital sample clock generator (SCG) for generating a sample clock signal (SCLK) from an input signal (FD) derived from a drive measurement voltage signal (DMV) of a vibrating MEMS gyroscope (VMEMS) is described. The sample clock generator (SCG) has an oscillator (HFOSC) arranged to generate a master clock (MOSC) with a master clock period, a synchronization unit (SYN) arranged to detect a start of an input signal period (FR_PER) of the input signal (FD) and to, upon detecting the start, generate a synchronization pulse (FD_OSC) in synchronization with the master clock (MOSC), ), a counter unit (OSCCNTR) arrange to count master clock periods between subsequent synchronization pulses to obtain the number of master clock periods between subsequent synchronization pulses as a number count, a multiplier (MULT) arranged to multiply the number count with a pre-determined phase shift fraction (PhPerc) to obtain a number of trim periods, and a delay unit (DLY) arranged to generate the sample clock signal (SLCK) with a clock signal period (SCLK_PER) corresponding to the number count (CNT) and with a delay relative to the synchronization pulse corresponding to the number of trim periods (TRM). A drive-mode vibration gyroscope circuitry (VDCIRC) and a sense-mode vibration gyroscope circuitry (VSCIRC) are also described.

Abstract translation: 描述了用于从由振动MEMS陀螺仪（VMEMS）的驱动测量电压信号（DMV）导出的输入信号（FD）产生采样时钟信号（SCLK）的数字采样时钟发生器（SCG）。 采样时钟发生器（SCG）具有被配置为产生具有主时钟周期的主时钟（MOSC）的振荡器（HFOSC），被配置为检测输入的输入信号周期（FR_PER）的开始的同步单元（SYN） 信号（FD），并且在检测到开始时，与主时钟（MOSC）同步地生成同步脉冲（FD_OSC）），计数单元（OSCCNTR），其配置为对后续同步脉冲之间的主时钟周期进行计数，以获得 在后续同步脉冲之间作为数字计数的主时钟周期数;乘法器（MULT），被布置为将数量乘以预定相移分数（PhPerc）以获得修剪周期数;以及延迟单元（DLY ），其被布置成以对应于数量计数（CNT）的时钟信号周期（SCLK_PER）并且相对于与修剪周期数（TRM）相对应的同步脉冲具有延迟来生成采样时钟信号（SLCK）。 还描述了驱动模式振动陀螺仪电路（VDCIRC）和感测模式振动陀螺仪电路（VSCIRC）。

公开(公告)号：WO2012050761A2

公开(公告)日：2012-04-19

申请号：PCT/US2011052331

申请日：2011-09-20

Applicant: DOW CORNING ,  HUPFIELD PETER ,  ZHOU XIAOBING

Inventor： HUPFIELD PETER ,  ZHOU XIAOBING

IPC: C07F7/08

CPC classification number: H03K21/00 ,  H03K21/026 ,  H03K21/12

Abstract: A process for preparing an acryloyloxysilane, the process comprising reacting a metal salt of a carboxylic acid having the formula [CR2 2=CR1COO-]aMa+ (I), with a haloorganoalkoxysilane having the formula XR3Si(OR4)nR5 3_n (II) in the presence of mineral spirits and a phase transfer catalyst at a temperature of from 50 to 160 °C to form a mixture comprising an acryloyloxysilane and a metal halide having the formula Ma+X- a (III), wherein R1 is H or C1 -C6 hydrocarbyl, each R2 is independently R1 or [COO-]aMa+, Ma+ is an alkali metal cation or alkaline earth metal cation, a is 1 or 2, X is halo, R3 is C1 -C6 hydrocarbylene, each R4 is independently C1 -C10 Q hydrocarbyl, each R5 is independently R1 and n is an integer from 1 to 3.

Abstract translation: 一种制备丙烯酰氧基硅烷的方法，该方法包括使具有式[CR2 2 = CR1COO-] aMa +（I）的羧酸的金属盐与式XR3Si（OR4）nR5 3_n（II）的卤代有机烷氧基硅烷在 在50至160℃的温度下存在矿物油精和相转移催化剂以形成包含丙烯酰氧基硅烷和具有式Ma + X-a-a（III）的金属卤化物的混合物，其中R 1为H或C 1 -C 6 烃基，每个R 2独立地是R 1或[COO-] a M a +，Ma +是碱金属阳离子或碱土金属阳离子，a是1或2，X是卤素，R 3是C 1 -C 6亚烃基，每个R 4独立地是C 1 -C 10 Q个烃基，每个R 5独立地为R 1，n为1至3的整数。

公开(公告)号：WO2012038736A1

公开(公告)日：2012-03-29

申请号：PCT/GB2011/051765

申请日：2011-09-20

Applicant: Novelda AS ,  GRANHAUG, Kristian ,  MEISAL, Kjetil ,  GARDINER, Stephen

Inventor： GRANHAUG, Kristian ,  MEISAL, Kjetil

IPC: H04B1/709 ,  G04F10/00 ,  H03M7/16 ,  H04L25/40 ,  H04B1/7163

CPC classification number: H03K5/14 ,  G01S7/2926 ,  G01S13/0209 ,  G01S13/18 ,  H03K5/22 ,  H03K21/00 ,  H03M7/165 ,  H04B1/709 ,  H04B1/71637 ,  H04L7/042

Abstract: A continuous time counter and method of counting are provided, comprising a sequence of adding stages which build up the output based on the inputs by progressively adding new values to opposite ends of an output stack. The counter provides for fast and reliable continuous time counting operations.

Abstract translation: 提供连续时间计数器和计数方法，其包括通过逐渐将新值添加到输出堆叠的相对端而基于输入来增加输出的级的序列。 该计数器提供快速可靠的连续计时操作。