Abstract:
A solid state imaging system has at least one CMOS imager (190) with first and second series of pixels (191, 192, 193) in which the pixels of one series are offset, i.e., staggered, in respect to the pixels of the other series. Multiple imagers can be arrayed end to end, with jumper wires (48) connecting the pixel output conductors or each so that the pixels feed into a common output amplifier (160, 161 ) for each series, to minimize chip to chip offset voltages. The pixels may be diagonally offset from one another, and a color imager can be constructed in which color ribbon filters are arranged diagonally across the imaging area. This arrangement minimizes color cross talk. An array of microlenses (200, 210, 210', 211) is situated with each microlens covering a plurality of the pixels. The pixels under each microlens can be aligned along a diagonal. The different pixels under the same microlens can have different integration times, to increase the dynamic range of the imager(s).
Abstract:
A solid state imaging system has at least one CMOS imager (190) with first and second series of pixels (191, 192, 193) in which the pixels of one series are offset, i.e., staggered, in respect to the pixels of the other series. Multiple imagers can be arrayed end to end, with jumper wires (48) connecting the pixel output conductors or each so that the pixels feed into a common output amplifier (160, 161 ) for each series, to minimize chip to chip offset voltages. The pixels may be diagonally offset from one another, and a color imager can be constructed in which color ribbon filters are arranged diagonally across the imaging area. This arrangement minimizes color cross talk. An array of microlenses (200, 210, 210', 211) is situated with each microlens covering a plurality of the pixels. The pixels under each microlens can be aligned along a diagonal. The different pixels under the same microlens can have different integration times, to increase the dynamic range of the imager(s).
Abstract:
A solid state imager converts analog pixel values to digital. A counter (16) coupled to an N-bit DAC (20) produces an analog ramp corresponding to the contents of the counter. A ripple counter (90, 92) is associated with each respective column. Column comparators (22) gate the counter elements when the analog ramp equals the pixel value. The counter contents feed a video output bus to produce the digital video signal. Additional black-level readout counters elements (26) can create and store a black level values for reduction of fixed pattern noise. Additional buffer counter/latches can be employed. Ripple counters can be configured as counters to capture the digital video level, and then as shift registers to clock out the video levels to an output bus. The clocks for the DAC counter and ripple counters can be at the same or different rates.