公开(公告)号：WO2012154507A1

公开(公告)日：2012-11-15

申请号：PCT/US2012/036370

申请日：2012-05-03

Applicant: RAMBUS INC. ,  BANSAL, Akash ,  FRANS, Yohan U. ,  KASAMSETTY, Kishore V. ,  BYSTROM, Todd ,  LI, Simon ,  VAIDYANATH, Arun

Inventor： BANSAL, Akash ,  FRANS, Yohan U. ,  KASAMSETTY, Kishore V. ,  BYSTROM, Todd ,  LI, Simon ,  VAIDYANATH, Arun

IPC: G11C7/00 ,  G06F1/04

CPC classification number: G11C7/22 ,  G06F1/10 ,  G11C7/222 ,  G11C29/023 ,  G11C29/028 ,  G11C2207/2254

Abstract: The disclosed embodiments related to a clocked memory system which performs a calibration operation at a full-rate frequency to determine a full-rate calibration state that specifies a delay between a clock signal and a corresponding data signal in the clocked memory system. Next, the clocked memory system uses the full-rate calibration state to calculate a sub-rate calibration state, which is associated with a sub-rate frequency (e.g., 1/2, 1/4 or 1/8 of the full-rate frequency). The system then uses this sub-rate calibration state when the clocked memory system is operating at the sub-rate frequency. This calculation of the sub-rate state calibration states eliminates the need to perform an additional time-consuming calibration operation for each sub-rate.

Abstract translation: 公开的实施例涉及一种时钟存储器系统，其以全速率频率执行校准操作，以确定指定时钟信号与时钟控制的存储器系统中相应的数据信号之间的延迟的全速率校准状态。 接下来，时钟存储器系统使用全速率校准状态来计算子速率校准状态，其与子速率频率（例如，全速率的1/2速率，1/4或1/8）相关联 频率）。 当时钟存储器系统以子速率频率工作时，系统然后使用该子速率校准状态。 子速率状态校准状态的这种计算消除了对每个子速率执行附加耗时的校准操作的需要。