公开(公告)号：WO2018017189A1

公开(公告)日：2018-01-25

申请号：PCT/US2017/034938

申请日：2017-05-30

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： TANG, Tianyu ,  RAMACHANDRA, Venkatesh ,  RAJENDRA, Srinivas

IPC: H03K5/14 ,  H03K5/156 ,  G11C13/00

CPC classification number: H03K5/1565 ,  G11C7/222 ,  G11C13/0021 ,  G11C13/003 ,  G11C13/004 ,  G11C13/0061 ,  G11C13/0069 ,  G11C16/0483 ,  G11C16/32 ,  G11C2207/2254 ,  G11C2213/71 ,  G11C2213/75 ,  G11C2213/77

Abstract: Systems and methods for generating periodic signals with reduced duty cycle variation are described. In some cases, a calibration procedure may be performed prior to a memory operation (e.g., prior to a read operation or a programming operation) in which a duty cycle correction circuit receives an input signal (e.g., an input clock signal), steps through various delay settings to determine a first delay setting corresponding with a signal high time for the input signal and a second delay setting corresponding with a signal low time for the input signal, generates a delayed version of the input signal corresponding with a mid-point delay setting between the first delay setting and the second delay setting, and generates a corrected signal using the delayed version of the input signal and the input signal.

Abstract translation: 描述了用于产生具有减小的占空比变化的周期性信号的系统和方法。 在一些情况下，可以在占空比校正电路接收输入信号（例如，输入时钟信号）的存储器操作之前（例如，在读取操作或编程操作之前）执行校准过程， 确定与输入信号的高信号时间对应的第一延迟设置和与输入信号的信号低时间对应的第二延迟设置的各种延迟设置生成与中点延迟对应的输入信号的延迟版本 设置在第一延迟设置和第二延迟设置之间，并且使用输入信号的延迟版本和输入信号产生校正信号。

公开(公告)号：WO2017100078A1

公开(公告)日：2017-06-15

申请号：PCT/US2016/064484

申请日：2016-12-01

Applicant: RAMBUS INC.

Inventor： WARE, Frederick, A. ,  LINSTADT, John, Eric ,  WERNER, Carl, W.

IPC: H04L12/931 ,  G06F1/32

CPC classification number: G06F1/12 ,  G11C7/04 ,  G11C7/222 ,  G11C29/022 ,  G11C29/023 ,  G11C29/50012 ,  G11C2207/2254 ,  H03K5/15

Abstract: In a chip-to-chip signaling system includes at least one signaling link coupled between first and second ICs, the first IC has an interface coupled to the signaling link and timed by a first interface timing signal. The second IC has an interface coupled to the signaling link and timed by a second interface timing signal that is mesochronous with respect to the first interface timing signal. The second IC further has phase adjustment circuitry that adjusts a phase of the second interface timing signal using a digital counter implemented with Josephson-junction circuit elements.

Abstract translation: 在芯片到芯片信令系统包括耦合在第一和第二IC之间的至少一个信令链路的情况下，第一IC具有耦合到信令链路并且由第一接口时序信号定时的接口。 第二IC具有耦合到信令链路的接口，并且通过相对于第一接口定时信号是中间的第二接口定时信号定时。 第二IC还具有相位调整电路，其使用用约瑟夫逊结电路元件实现的数字计数器来调整第二接口定时信号的相位。

公开(公告)号：WO2016187221A1

公开(公告)日：2016-11-24

申请号：PCT/US2016/032912

申请日：2016-05-17

Applicant: MICRON TECHNOLOGY, INC

Inventor： SHIDO, Taihei

IPC: G11C11/406 ,  G11C11/4076 ,  G11C7/22 ,  G11C5/06

CPC classification number: G11C11/406 ,  G11C7/222 ,  G11C11/40603 ,  G11C11/4076 ,  G11C11/4087 ,  G11C11/4093

Abstract: Some embodiments include an apparatus that comprise an interface chip having an oscillator to produce an original clock signal, a first memory chip having first memory cells, and a second memory chip having second memory cells. The first memory cells may be refreshed in response to a first clock signal based on the original clock signal. The second memory cells may be refreshed in response to a second clock signal based on the original clock signal.

Abstract translation: 一些实施例包括一种装置，其包括具有产生原始时钟信号的振荡器的接口芯片，具有第一存储器单元的第一存储器芯片和具有第二存储器单元的第二存储器芯片。 可以响应于基于原始时钟信号的第一时钟信号来刷新第一存储器单元。 响应于基于原始时钟信号的第二时钟信号可以刷新第二存储器单元。

公开(公告)号：WO2016099681A1

公开(公告)日：2016-06-23

申请号：PCT/US2015/058832

申请日：2015-11-03

Applicant: MICRON TECHNOLOGY, INC.

Inventor： NAM, Ki-Jun ,  PORTER, John David

IPC: G11C7/10 ,  G11C7/22

CPC classification number: G11C7/1012 ,  G11C7/00 ,  G11C7/10 ,  G11C7/106 ,  G11C7/1087 ,  G11C7/1093 ,  G11C7/22 ,  G11C7/222 ,  G11C8/00 ,  G11C8/18 ,  G11C2207/107 ,  H03K3/017 ,  H03K5/1502 ,  H03L7/06

Abstract: Apparatuses and methods for capturing data using a divided clock are described. An example apparatus includes a clock divider configured to receive a DQS signal, and to provide divided clock signals. A divided clock signal of the divided clock signals has a frequency that is less than a frequency of the DQS signal. The example apparatus further includes a command circuit configured to receive a command, and to assert one of a plurality of flag signals based on the divided clock signals and on a defined latency from a time of receipt of the command. The example apparatus further includes a data capture circuit configured serially receive data associated with the command and to provide deserialized data responsive to the divided clock signals. The data capture circuit is further configured to sort the deserialized data based on the asserted one of the plurality of flag signals to provide sorted data.

Abstract translation: 描述了使用分时钟捕获数据的装置和方法。 示例性装置包括被配置为接收DQS信号并且提供分频时钟信号的时钟分配器。 分频时钟信号的分频时钟信号的频率小于DQS信号的频率。 该示例设备还包括命令电路，其被配置为接收命令，并且基于所划分的时钟信号以及从接收到该命令的时间开始确定的延迟来断言多个标志信号之一。 该示例设备还包括数据捕获电路，其配置为串行地接收与该命令相关联的数据，并且响应于划分的时钟信号来提供反序列化数据。 数据捕获电路还被配置为基于所述多个标志信号中的所述一个标记信号对反序列化数据进行排序以提供分类数据。

公开(公告)号：WO2016043844A1

公开(公告)日：2016-03-24

申请号：PCT/US2015/041587

申请日：2015-07-22

Applicant: QUALCOMM INCORPORATED

Inventor： SINGH, Guneet ,  CHENG, Yuehchun Claire ,  DIFFENDERFER, Jan Christian ,  SRINIVAS, Vaishnav ,  KIM, Robert Won Chol

IPC: G11C7/10 ,  G11C11/4076 ,  G11C29/02 ,  G11C7/22

CPC classification number: H03K5/13 ,  G11C7/1066 ,  G11C7/1093 ,  G11C7/222 ,  G11C11/4076 ,  G11C29/023 ,  G11C29/028 ,  H03K2005/00019

Abstract: Systems and methods for delay control are described herein. In one embodiment, a delay circuit comprises a first delay path and a second delay path. The delay circuit also comprises a plurality of switches, wherein each switch is coupled between different points on the first and second delay paths, and each switch is configured to turn on or off in response to a respective one of a plurality of select signals. The delay circuit further comprises a multiplexer having a first input coupled to an output of the first delay path, a second input coupled to an output of the second delay path, and an output coupled to an output of the delay circuit, wherein the multiplexer is configured to selectively couple one of the outputs of the first and second delay paths to the output of the delay circuit in response to a second select signal.

Abstract translation: 本文描述了用于延迟控制的系统和方法。 在一个实施例中，延迟电路包括第一延迟路径和第二延迟路径。 延迟电路还包括多个开关，其中每个开关耦合在第一和第二延迟路径上的不同点之间，并且每个开关被配置为响应于多个选择信号中的相应一个而导通或关断。 延迟电路还包括多路复用器，其具有耦合到第一延迟路径的输出的第一输入，耦合到第二延迟路径的输出的第二输入和耦合到延迟电路的输出的输出，其中多路复用器是 被配置为响应于第二选择信号选择性地将第一和第二延迟路径的输出之一耦合到延迟电路的输出。

公开(公告)号：WO2014143056A1

公开(公告)日：2014-09-18

申请号：PCT/US2013/032633

申请日：2013-03-15

Applicant: INTEL CORPORATION ,  NALE, Bill ,  JASPER, Jonathan C. ,  LOVELACE, John V. ,  NACHIMUTHU, Murugasamy K. ,  ZHU, Jun ,  QUACH, Tuan M.

Inventor： NALE, Bill ,  JASPER, Jonathan C. ,  LOVELACE, John V. ,  NACHIMUTHU, Murugasamy K. ,  ZHU, Jun ,  QUACH, Tuan M.

IPC: G11C7/10 ,  G11C7/22 ,  G06F13/14

CPC classification number: G06F11/0793 ,  G06F3/0604 ,  G06F3/061 ,  G06F3/0629 ,  G06F3/0638 ,  G06F3/0673 ,  G06F3/0683 ,  G06F11/0727 ,  G06F11/0751 ,  G06F11/0772 ,  G06F11/079 ,  G06F12/023 ,  G06F12/0802 ,  G06F12/0813 ,  G06F13/1663 ,  G06F13/1678 ,  G06F13/1689 ,  G06F13/1694 ,  G06F13/4234 ,  G06F13/4243 ,  G06F13/4282 ,  G06F2212/1044 ,  G06F2212/2532 ,  G06F2212/60 ,  G11C5/04 ,  G11C5/148 ,  G11C7/1003 ,  G11C7/1063 ,  G11C7/1072 ,  G11C7/222 ,  G11C11/40618 ,  G11C29/023 ,  G11C29/028 ,  H04L9/0869

Abstract: Provided is a device for use in a memory module coupled to a host memory controller over a bus, comprising memory module control logic to generate a request signal to a host memory controller having a pulse width greater than or equal to a minimum pulse width, wherein the minimum pulse width comprises a number of clock cycles needed to guarantee that the host memory controller detects the request signal, and wherein the pulse width of the request signal indicates at least one function in addition to the request signal to the host memory controller.

Abstract translation: 提供了一种用于通过总线耦合到主机存储器控制器的存储器模块中的装置，包括存储器模块控制逻辑，以产生具有大于或等于最小脉冲宽度的脉冲宽度的主机存储器控制器的请求信号，其中 最小脉冲宽度包括保证主机存储器控制器检测到请求信号所需的多个时钟周期，并且其中请求信号的脉冲宽度除了向主机存储器控制器的请求信号之外还指示至少一个功能。

公开(公告)号：WO2014112453A1

公开(公告)日：2014-07-24

申请号：PCT/JP2014/050398

申请日：2014-01-14

Applicant: ピーエスフォー ルクスコ エスエイアールエル ,  太田 賢

Inventor： 太田　賢

IPC: G11C11/401 ,  G11C11/4093 ,  H01L21/822 ,  H01L27/04 ,  H03K19/0175

CPC classification number: H03K19/018557 ,  G11C7/1072 ,  G11C7/222 ,  G11C11/4076 ,  G11C11/4093 ,  H04L25/0278

Abstract: 　半導体装置は、入出力パッドと、入出力パッドにその一端が接続された第１の抵抗素子と、第１の抵抗素子の他端に接続され、第１の抵抗素子を介して入出力パッドへ出力信号を出力する第１の出力回路と、第１の抵抗素子の他端に接続され、第１の抵抗素子を介して入出力パッドから入力信号を受ける入力回路とを含む。

Abstract translation: 所述半导体器件包括输入/​​输出焊盘，具有连接到所述输入/输出焊盘的一端的第一电阻元件，用于经由所述第一电阻元件将输出信号输出到所述输入/输出焊盘并连接到所述第二电阻元件的第一输出电路 第一电阻元件的端部和用于经由第一电阻元件接收来自输入/输出焊盘的输入信号并连接到第一电阻元件的另一端的输入电路。

公开(公告)号：WO2014105262A1

公开(公告)日：2014-07-03

申请号：PCT/US2013/066821

申请日：2013-10-25

Applicant: SANDISK TECHNOLOGIES INC. ,  BHUIYAN, Ekram H.

Inventor： BHUIYAN, Ekram H.

IPC: G11C7/22 ,  G11C16/32 ,  G06F1/08

CPC classification number: H03K5/131 ,  G06F1/04 ,  G11C7/222 ,  G11C16/32

Abstract: This disclosure provides examples of circuits, devices, systems, and methods for generating a reference clock signal and delaying a received clock signal based on the reference clock signal. In one implementation, a circuit includes a control block configured to generate a control signal. The circuit includes an oscillator configured to generate a reference clock signal. The oscillator includes a plurality of delay elements each configured to receive the control signal and to introduce a delay in the reference clock signal based on the control signal. The delay elements of the oscillator are arranged to generate the reference clock signal. The circuit further includes a delay block configured to receive a clock signal and to generate a delayed clock signal. The delay block includes one or more delay elements each configured to receive the control signal and to introduce a delay in the clock signal based on the control signal.

Abstract translation: 本公开提供了用于基于参考时钟信号产生参考时钟信号和延迟接收的时钟信号的电路，设备，系统和方法的示例。 在一个实现中，电路包括被配置为产生控制信号的控制块。 电路包括配置成产生参考时钟信号的振荡器。 振荡器包括多个延迟元件，每个延迟元件被配置为接收控制信号并且基于控制信号在基准时钟信号中引入延迟。 振荡器的延迟元件被布置成产生参考时钟信号。 电路还包括被配置为接收时钟信号并产生延迟的时钟信号的延迟块。 延迟块包括一个或多个延迟元件，每个延迟元件被配置为接收控制信号并且基于控制信号在时钟信号中引入延迟。

公开(公告)号：WO2013025262A3

公开(公告)日：2014-05-08

申请号：PCT/US2012032645

申请日：2012-04-06

Applicant: CYPRESS SEMICONDUCTOR ,  MAHESHWARI DINESH ,  BARBARA BRUCE ,  MARINO JOHN

Inventor： MAHESHWARI DINESH ,  BARBARA BRUCE ,  MARINO JOHN

IPC: G06F13/00

CPC classification number: G11C11/4076 ,  G11C7/1039 ,  G11C7/1075 ,  G11C7/1087 ,  G11C7/1093 ,  G11C7/22 ,  G11C7/222 ,  G11C8/12 ,  G11C8/16 ,  G11C8/18 ,  G11C11/408 ,  G11C11/418 ,  G11C11/419

Abstract: A memory device can include a plurality of double data rate data (DDR) ports, each configured to receive write data and output read data on a same set of data lines independently and concurrently in synchronism with at least a first clock signal; an address port configured to receive address values on consecutive, different transitions of a second clock, each address value corresponding to an access on a different one of the data ports; and a memory array section comprising a plurality of banks, each bank providing pipelined access to storage locations therein.

Abstract translation: 存储器设备可以包括多个双数据速率数据（DDR）端口，每个双重数据速率数据（DDR）端口被配置为在至少第一时钟信号的同时独立地并行地接收写入数据并在同一组数据线上输出读取数据; 地址端口，被配置为在第二时钟的连续不同转换上接收地址值，每个地址值对应于在不同的数据端口上的访问; 以及包括多个存储体的存储器阵列部分，每个存储体提供对其中的存储位置的流水线访问。

公开(公告)号：WO2014008002A1

公开(公告)日：2014-01-09

申请号：PCT/US2013/046924

申请日：2013-06-20

Applicant: QUALCOMM INCORPORATED

Inventor： TERROVITIS, Emmanouil

IPC: G11C7/22 ,  H03L7/099

CPC classification number: H03L7/0891 ,  G11C7/222 ,  H03L7/099 ,  H03L7/16

Abstract: A delay-locked loop (DLL) circuit is disclosed that can generate an output oscillation signal having a frequency that is an integer multiple of an input oscillation signal. The DLL includes a phase detector, a charge pump, and a voltage-controlled oscillator (VCO). The phase detector generates UP and DN control signals in response to a phase difference between a reference signal and a feedback signal. The charge pump generates a control voltage in response to the UP and DN control signals. The VCO adjusts the frequency of the output oscillation signal in response to the control voltage, generates the reference signal in response to the input oscillation signal, and generates the feedback signal in response to the output oscillation signal.

Abstract translation: 公开了延迟锁定环路（DLL）电路，其可以产生具有输入振荡信号的整数倍的频率的输出振荡信号。 该DLL包括相位检测器，电荷泵和压控振荡器（VCO）。 相位检测器响应于参考信号和反馈信号之间的相位差产生UP和DN控制信号。 电荷泵响应于UP和DN控制信号产生控制电压。 VCO根据控制电压调节输出振荡信号的频率，响应于输入振荡信号产生参考信号，并根据输出振荡信号产生反馈信号。