Abstract:
Apparatus and methods for controlling sleep mode in a wireless device are disclosed. The sleep mode is controlled using low power detection of RF beacon signals of known frequencies to reduce power consumption of the wireless device during sleep modes. Detection is achieved by using passive or low power elements in a receive chain that filters received signals allowing beacon signals of particular frequencies to pass,which are accumulated with passive or low power circuit elements requiring no external power source. The accumulated energy is compared to a threshold to determine the presence of the beacon with sleep circuitry. When the beacon is detected, the full RF receiver is triggered to wake up. Use of low power elements and passive elements, affords a beneficial increase in power savings for the wireless device, which is particularly helpful in wireless access points or relay stations that have an alternative power sourcing such as battery or solar power.
Abstract:
Apparatus and methods for controlling sleep mode in a wireless device are disclosed. The sleep mode is controlled using low power detection of RF beacon signals of known frequencies to reduce power consumption of the wireless device during sleep modes. Detection is achieved by using passive or low power elements in a receive chain that filters received signals allowing beacon signals of particular frequencies to pass,which are accumulated with passive or low power circuit elements requiring no external power source. The accumulated energy is compared to a threshold to determine the presence of the beacon with sleep circuitry. When the beacon is detected, the full RF receiver is triggered to wake up. Use of low power elements and passive elements, affords a beneficial increase in power savings for the wireless device, which is particularly helpful in wireless access points or relay stations that have an alternative power sourcing such as battery or solar power.
Abstract:
Techniques for reducing or eliminating DC (direct current) offset in transmitters are disclosed. An apparatus for DC offset reduction may include a converter, a digital engine, and a plurality of programmable current supplies. The converter is configured to provide digital representations of a plurality of DC currents associated, respectively, with a plurality of differential signal legs. The digital engine is configured to receive the digital representations and to produce instructions for generating compensating currents for the plurality of differential signal legs based on comparisons, respectively, between each of the digital representations and a calibration current. The programmable current supplies correspond, respectively, to the differential signal legs. The current supplies are configured to inject the compensating currents into the differential signal legs, respectively, to reduce DC offset between the differential signal legs, based upon the instructions. The instructions allow one-shot DC offset correction, instead of successive approximation for DC offset correction.
Abstract:
An RF transceiver integrated circuit has a novel segmented, low parasitic capacitance, internal loopback conductor usable for conducting IP2 self testing and/or calibration. In a first novel aspect, the transmit mixer of the transceiver is a current mode output mixer. The receive mixer is a passive mixer that has a low input impedance. In the loopback mode, the transmit mixer drives a two tone current signal to the passive mixer via the loopback conductor. In a second novel aspect, only one quadrature branch of the transmit mixer is used to generate both tones required for carrying out an IP2 test. In a third novel aspect, a first calibration test is performed using one quadrature branch of the transmit mixer at the same time that a second calibration test is performed using the other quadrature branch, thereby reducing loopback test time and power consumption.
Abstract:
A driver amplifier in an integrated circuit is suitable for driving a signal onto an output node and through an output terminal, and through a matching network to a power amplifier. A novel Programmable Output Impedance Adjustment Circuit (POIAC) within the integrated circuit is coupled to the output node and affects an output impedance looking into the output terminal. When the output impedance would otherwise change (for example, due to a driver amplifier power gain change), the POIAC adjusts how it loads the output node such that the output impedance remains substantially constant. The POIAC uses a series-connected inductor and capacitor L-C-R circuit to load the output node, thereby reducing the amount of capacitance and die area required to perform multi-band impedance matching with a power amplifier. Multi-band operation is accomplished by changing an effective capacitance in the L-C-R circuit depending on communication band information received by the POIAC.