公开(公告)号：WO0175587A3

公开(公告)日：2002-01-24

申请号：PCT/US0110603

申请日：2001-04-02

Applicant: INTEL CORP ,  ANALOG DEVICES INC ,  KOLAGOTLA RAVI ,  ALDRICH BRADLEY C ,  ANDERSON WILLIAM C

Inventor： KOLAGOTLA RAVI ,  ALDRICH BRADLEY C ,  ANDERSON WILLIAM C

IPC: G06F7/50 ,  G06F7/52 ,  G06F7/53 ,  G06F7/57 ,  G06F7/48

CPC classification number: G06F7/57 ,  G06F7/509 ,  G06F7/53 ,  G06F2207/382 ,  G06F2207/3828

Abstract: In one embodiment, a dual mode execution unit is described for use in a general purpose digital signal processor (DSP). The execution unit can operate as a 16X16 multiplier in one mode and an 8-bit adder tree in another mode. The adder tree structure is constructed by reutilizing pre-existing arithmetic logic units (ALUs) in the multiplier array of the multiplier architecture. The 8-bit adder tree mode is particularly useful for performing various computation intensive algorithms used in digital video processing, such as motion search and spatial interpolation algorithms.

Abstract translation: 在一个实施例中，描述了用于通用数字信号处理器（DSP）中的双模执行单元。 执行单元可以在一种模式下作为16X16乘法器工作，另一种模式可以作为8位加法器树。 加法器树结构通过在乘法器架构的乘法器阵列中重新利用预先存在的算术逻辑单元（ALU）来构造。 8位加法器树模式对于执行诸如运动搜索和空间插值算法的数字视频处理中使用的各种计算密集型算法特别有用。

公开(公告)号：WO0174134A2

公开(公告)日：2001-10-11

申请号：PCT/US0110299

申请日：2001-03-30

Applicant: INTEL CORP ,  RAMAGOPAL HEBBALALU S ,  WITT DAVID B ,  ALLEN MICHAEL ,  SYED MOINUL ,  KOLAGOTLA RAVI ,  BOOTH LAWRENCE A JR ,  ANDERSON WILLIAM C

Inventor： RAMAGOPAL HEBBALALU S ,  WITT DAVID B ,  ALLEN MICHAEL ,  SYED MOINUL ,  KOLAGOTLA RAVI ,  BOOTH LAWRENCE A JR ,  ANDERSON WILLIAM C

IPC: G06F12/08 ,  G06F13/16

CPC classification number: G06F12/0855 ,  G06F12/0893 ,  G06F13/16

Abstract: An apparatus having a core processor and a memory system is disclosed. The core processor includes at least one data port. The memory system is connected in such a way as to provide substantially simultaneous data accesses through the data port. The memory system can be made user configurable to provide appropriate memory model.

Abstract translation: 公开了一种具有核心处理器和存储器系统的设备。 核心处理器包括至少一个数据端口。 存储器系统以这样的方式连接，以便通过数据端口提供基本上同时的数据访问。 存储器系统可以由用户配置来提供适当的存储器模型。

公开(公告)号：WO2013006512A3

公开(公告)日：2013-06-06

申请号：PCT/US2012045155

申请日：2012-06-30

Applicant: INTEL CORP ,  CHANG YUH-LIN E ,  KOLAGOTLA RAVI ,  ATHREYA MADHU S

Inventor： CHANG YUH-LIN E ,  KOLAGOTLA RAVI ,  ATHREYA MADHU S

IPC: G06F17/00 ,  G06F1/32

CPC classification number: H04N5/23241 ,  G06F1/3287 ,  H04N5/2176 ,  H04N5/23206 ,  H04N9/045 ,  Y02D10/171

Abstract: Methods and apparatus relating to an image signal processor architecture that may be optimized for low-power consumption, processing flexibility, and/or user experience are described. In an embodiment, an image signal processor may be partitioned into a plurality of partitions. Each partition may be capable of entering a lower power consumption state. Also, processing by each partition may be done in various modes to optimize for low-power consumption, processing flexibility, and/or user experience. Other embodiments are also disclosed and claimed.

Abstract translation: 描述可针对低功耗，处理灵活性和/或用户体验优化的与图像信号处理器架构有关的方法和设备。 在一个实施例中，图像信号处理器可以被分割成多个分区。 每个分区可以能够进入较低的功耗状态。 而且，每个分区的处理可以以各种模式完成，以优化低功耗，处理灵活性和/或用户体验。 其他实施例也被公开和要求保护。

公开(公告)号：WO2013006512A2

公开(公告)日：2013-01-10

申请号：PCT/US2012/045155

申请日：2012-06-30

Applicant: INTEL CORPORATION ,  CHANG, Yuh-Lin E. ,  KOLAGOTLA, Ravi ,  ATHREYA, Madhu S.

Inventor： CHANG, Yuh-Lin E. ,  KOLAGOTLA, Ravi ,  ATHREYA, Madhu S.

CPC classification number: H04N5/23241 ,  G06F1/3287 ,  H04N5/2176 ,  H04N5/23206 ,  H04N9/045 ,  Y02D10/171

Abstract: Methods and apparatus relating to an image signal processor architecture that may be optimized for low-power consumption, processing flexibility, and/or user experience are described. In an embodiment, an image signal processor may be partitioned into a plurality of partitions. Each partition may be capable of entering a lower power consumption state. Also, processing by each partition may be done in various modes to optimize for low-power consumption, processing flexibility, and/or user experience. Other embodiments are also disclosed and claimed.

Abstract translation: 描述了可以针对低功耗，处理灵活性和/或用户体验而优化的图像信号处理器架构的方法和装置。 在一个实施例中，图像信号处理器可以被划分成多个分区。 每个分区可能能够进入较低的功耗状态。 此外，每个分区的处理可以以各种模式进行，以优化低功耗，处理灵活性和/或用户体验。 还公开并要求保护其他实施例。