公开(公告)号：WO2007090008A2

公开(公告)日：2007-08-09

申请号：PCT/US2007060903

申请日：2007-01-23

Applicant: MOTOROLA INC ,  FREI JEFFREY A ,  KRVAVAC ENVER

Inventor： FREI JEFFREY A ,  KRVAVAC ENVER

IPC: H03F3/191

CPC classification number: H03F1/56 ,  H03F1/52 ,  H03F3/191 ,  H03F3/193 ,  H03F2200/387 ,  H03F2200/391 ,  H03F2200/451 ,  H03F2203/21139 ,  H03H7/38

Abstract: Power amplifier (PA) apparatus (300) that includes: a PA device (302) operating at a fundamental frequency and having a maximum operating frequency that is higher than the fundamental frequency, an output current having a fundamental component at the fundamental frequency and a plurality of harmonic components at different harmonic frequencies of the fundamental frequency, and an output voltage based on the output current; a first matching circuit (310) coupled to the PA device and corresponding to the fundamental component; and a second matching circuit (320) coupled between the PA device and the first matching circuit and corresponding to at least one of the harmonic components, wherein the first and second matching circuits maintain the PA output voltage at a value that is no more than a predetermined maximum value, which is less than a breakdown voltage for the PA device.

Abstract translation: 功率放大器（PA）装置（300）包括：以基频工作的具有高于基频的最大工作频率的PA装置（302），具有基频的基波分量的输出电流和 在基频的不同谐波频率下的多个谐波分量和基于输出电流的输出电压; 第一匹配电路（310），其耦合到所述PA设备并对应于所述基本分量; 以及耦合在PA设备和第一匹配电路之间并对应于至少一个谐波分量的第二匹配电路（320），其中第一和第二匹配电路将PA输出电压保持在不大于 预定的最大值小于PA器件的击穿电压。

公开(公告)号：WO2009045686A3

公开(公告)日：2010-07-22

申请号：PCT/US2008075744

申请日：2008-09-10

Applicant: MOTOROLA INC ,  KRVAVAC ENVER

Inventor： KRVAVAC ENVER

IPC: H03F1/07

CPC classification number: H03F1/0288 ,  H03F2200/451

Abstract: An amplifier (100) that amplifies an input signal and provides the amplified signal to a load (114) at a summing junction (110) that has a first impedance value. The amplifier includes a splitter network (102) receiving the input signal and providing a phase delayed signal and an undelayed signal; a carrier amplifier path amplifying the phase delayed signal and including a carrier amplifier (106) and a first output match network (108) coupled between the carrier amplifier and the summing node; and a peaking amplifier path amplifying the undelayed signal and including a peaking amplifier (118), a second output match network (120) coupled to the peaking amplifier, and a phase delay element (122) coupled between the second output match network and the summing node, wherein the phase delay element provides a degree of phase delay and has a designed characteristic impedance value that is larger than the first impedance value for increasing the off-state impedance of the peaking amplifier.

Abstract translation: 放大器（100），其放大输入信号并将放大的信号提供给具有第一阻抗值的求和结（110）处的负载（114）。 放大器包括接收输入信号并提供相位延迟信号和未延迟信号的分路器网络（102） 载波放大器路径，其放大所述相位延迟信号，并且包括耦合在所述载波放大器和所述求和节点之间的载波放大器（106）和第一输出匹配网络（108） 以及放大所述未延迟信号并包括峰化放大器（118）的峰化放大器路径，耦合到所述峰化放大器的第二输出匹配网络（120）以及耦合在所述第二输出匹配网络和所述求和 节点，其中所述相位延迟元件提供一定程度的相位延迟，并且具有大于所述第一阻抗值的设计特征阻抗值，以增加所述峰化放大器的截止阻抗。

公开(公告)号：WO2005104355A1

公开(公告)日：2005-11-03

申请号：PCT/US2005/002494

申请日：2005-01-26

Applicant: FREESCALE SEMICONDUCTOR, INC. ,  KRVAVAC, Enver ,  MITZLAFF, James, E. ,  VAN HORN, Mark, I.

Inventor： KRVAVAC, Enver ,  MITZLAFF, James, E. ,  VAN HORN, Mark, I.

IPC: H03F3/04

CPC classification number: H03F1/0288 ,  H03F1/301 ,  H03F3/04 ,  H03F2200/18 ,  H03F2200/366 ,  H03F2200/75

Abstract: Apparatus and methods are described for biasing amplifiers with multiple outputs. A semiconductor die (100) may include a reference Field Effect Transistor (FET) (112) integrated on the semiconductor die and coupled to an amplifier (116) integrated on the semiconductor die. A voltage offset circuit (114) may also be integrated on the semiconductor die (100) for determining the voltage needed to operate the amplifier (116).

Abstract translation: 描述用于具有多个输出的偏置放大器的装置和方法。 半导体管芯（100）可以包括集成在半导体管芯上并耦合到集成在半导体管芯上的放大器（116）的参考场效应晶体管（FET）（112）。 电压偏移电路（114）也可以集成在半导体管芯（100）上，用于确定操作放大器（116）所需的电压。

公开(公告)号：WO2007090008A3

公开(公告)日：2007-08-09

申请号：PCT/US2007/060903

申请日：2007-01-23

Applicant: MOTOROLA, INC. ,  FREI, Jeffrey A., ,  KRVAVAC, Enver,

Inventor： FREI, Jeffrey A., ,  KRVAVAC, Enver,

IPC: H03F3/04

Abstract: Power amplifier (PA) apparatus (300) that includes: a PA device (302) operating at a fundamental frequency and having a maximum operating frequency that is higher than the fundamental frequency, an output current having a fundamental component at the fundamental frequency and a plurality of harmonic components at different harmonic frequencies of the fundamental frequency, and an output voltage based on the output current; a first matching circuit (310) coupled to the PA device and corresponding to the fundamental component; and a second matching circuit (320) coupled between the PA device and the first matching circuit and corresponding to at least one of the harmonic components, wherein the first and second matching circuits maintain the PA output voltage at a value that is no more than a predetermined maximum value, which is less than a breakdown voltage for the PA device.

公开(公告)号：WO2007044148A3

公开(公告)日：2007-04-19

申请号：PCT/US2006/033664

申请日：2006-08-28

Applicant: MOTOROLA, INC. ,  KRVAVAC, Enver, ,  SCHULTZ, Joseph G., ,  YU, Yinglei,

Inventor： KRVAVAC, Enver, ,  SCHULTZ, Joseph G., ,  YU, Yinglei,

IPC: H03F3/68 ,  H03F3/20 ,  H01Q11/12

Abstract: An apparatus and method for adaptive biasing of a Doherty amplifier (102) is disclosed. The apparatus includes a carrier amplifier (210), a peaking amplifier (214), a carrier amplifier bias circuit (208) and a peaking amplifier bias circuit (212), all integrated onto a single chip. The method includes dividing an input signal into an in-phase signal and a quadrature phase signal. The method further includes sampling the input signal and applying the sampled signal to the biasing circuits. The method further includes adaptively biasing the carrier amplifier and the peaking amplifier by the output of the biasing circuits.

公开(公告)号：WO2009045686A2

公开(公告)日：2009-04-09

申请号：PCT/US2008/075744

申请日：2008-09-10

Applicant: MOTOROLA, INC. ,  KRVAVAC, Enver,

Inventor： KRVAVAC, Enver,

IPC: H03F1/07

CPC classification number: H03F1/0288 ,  H03F2200/451

Abstract: An amplifier (100) that amplifies an input signal and provides the amplified signal to a load (114) at a summing junction (110) that has a first impedance value. The amplifier includes a splitter network (102) receiving the input signal and providing a phase delayed signal and an undelayed signal; a carrier amplifier path amplifying the phase delayed signal and including a carrier amplifier (106) and a first output match network (108) coupled between the carrier amplifier and the summing node; and a peaking amplifier path amplifying the undelayed signal and including a peaking amplifier (118), a second output match network (120) coupled to the peaking amplifier, and a phase delay element (122) coupled between the second output match network and the summing node, wherein the phase delay element provides a degree of phase delay and has a designed characteristic impedance value that is larger than the first impedance value for increasing the off-state impedance of the peaking amplifier.

Abstract translation: 放大器（100），其放大输入信号并将放大的信号提供给具有第一阻抗值的求和结（110）处的负载（114）。 放大器包括接收输入信号并提供相位延迟信号和未延迟信号的分路器网络（102） 载波放大器路径，其放大所述相位延迟信号，并且包括耦合在所述载波放大器和所述求和节点之间的载波放大器（106）和第一输出匹配网络（108） 以及放大所述未延迟信号并包括峰化放大器（118）的峰化放大器路径，耦合到所述峰化放大器的第二输出匹配网络（120）以及耦合在所述第二输出匹配网络和所述求和 节点，其中所述相位延迟元件提供一定程度的相位延迟，并且具有大于所述第一阻抗值的设计特征阻抗值，以增加所述峰化放大器的截止阻抗。

公开(公告)号：WO2007044148A2

公开(公告)日：2007-04-19

申请号：PCT/US2006033664

申请日：2006-08-28

Applicant: MOTOROLA INC ,  KRVAVAC ENVER ,  SCHULTZ JOSEPH G ,  YU YINGLEI

Inventor： KRVAVAC ENVER ,  SCHULTZ JOSEPH G ,  YU YINGLEI

IPC: H03F3/68

CPC classification number: H03F1/30 ,  H03F1/0288 ,  H03F2200/18

Abstract: An apparatus and method for adaptive biasing of a Doherty amplifier (102) is disclosed. The apparatus includes a carrier amplifier (210), a peaking amplifier (214), a carrier amplifier bias circuit (208) and a peaking amplifier bias circuit (212), all integrated onto a single chip. The method includes dividing an input signal into an in-phase signal and a quadrature phase signal. The method further includes sampling the input signal and applying the sampled signal to the biasing circuits. The method further includes adaptively biasing the carrier amplifier and the peaking amplifier by the output of the biasing circuits.

Abstract translation: 公开了一种用于Doherty放大器（102）的自适应偏置的装置和方法。 该装置包括载波放大器（210），峰化放大器（214），载波放大器偏置电路（208）和峰值放大器偏置电路（212），它们都集成到单个芯片上。 该方法包括将输入信号分成同相信号和正交相位信号。 该方法还包括对输入信号进行采样并将采样信号施加到偏置电路。 该方法还包括通过偏置电路的输出自适应地偏置载波放大器和峰值放大器。