公开(公告)号：WO2007133893A1

公开(公告)日：2007-11-22

申请号：PCT/US2007/067134

申请日：2007-04-20

Applicant: QUALCOMM Incorporated ,  PLONDKE, Erich ,  LESTER, Robert, Allan ,  CODRESCU, Lucian ,  AHMED, Muhammad

Inventor： PLONDKE, Erich ,  LESTER, Robert, Allan ,  CODRESCU, Lucian ,  AHMED, Muhammad

IPC: G06F9/30 ,  G06F9/38

CPC classification number: G06F9/30149 ,  G06F9/325 ,  G06F9/3853 ,  G06F9/3885

Abstract: Methods and apparatus for encoding information regarding a hardware loop of a set of packets is provided, each packet (400) containing instructions. The information is encoded into one or more bits of at least one instruction (300) in the set of packets. The information may indicate whether a packet is or is not an end packet of the loop. Information regarding two hardware loops may be encoded where information regarding the first loop is encoded into an instruction at a first position in each packet and information regarding the second loop is encoded into an instruction at a second position in each packet. End instruction information may be encoded into an instruction not having encoded loop information at the same bit positions reserved for the encoded loop information, the end instruction information indicating whether an instruction is the last instruction of a packet and the length of a packet.

Abstract translation: 提供了用于编码关于一组分组的硬件循环的信息的方法和装置，每个分组（400）包含指令。 信息被编码成该组分组中的至少一个指令（300）的一个或多个位。 信息可以指示分组是否是循环的结束分组。 关于两个硬件循环的信息可以被编码，其中关于第一循环的信息被编码为每个分组中的第一位置处的指令，并且关于第二循环的信息被编码为每个分组中的第二位置处的指令。 结束指令信息可以被编码为在编码环路信息保留的相同位位置处不具有编码环路信息的指令，表示指令是分组的最后指令还是分组长度的结束指令信息。

公开(公告)号：WO2006110886A3

公开(公告)日：2007-03-29

申请号：PCT/US2006013948

申请日：2006-04-11

Applicant: QUALCOMM INC ,  AHMED MUHAMMAD ,  CODRESCU LUCIAN ,  PLONDKE ERICH ,  ANDERSON WILLIAM C ,  LESTER ROBERT ALLAN ,  JONES PHILLIP M

Inventor： AHMED MUHAMMAD ,  CODRESCU LUCIAN ,  PLONDKE ERICH ,  ANDERSON WILLIAM C ,  LESTER ROBERT ALLAN ,  JONES PHILLIP M

IPC: G06F9/38

CPC classification number: G06F9/325 ,  G06F9/3802 ,  G06F9/3804 ,  G06F9/381

Abstract: An instruction memory unit comprises a first memory structure operable to store program instructions, and a second memory structure operable to store program instructions fetched from the first memory structure, and to issue stored program instructions for execution. The second memory structure is operable to identify a repeated issuance of a forward program redirect construct, and issue a next program instruction already stored in the second memory structure if a resolution of the forward branching instruction is identical to a last resolution of the same. The second memory structure is further operable to issue a backward program redirect construct, determine whether a target instruction is stored in the second memory structure, issue the target instruction if the target instruction is stored in the second memory structure, and fetch the target instruction from the first memory structure if the target instruction is not stored in the second memory structure.

Abstract translation: 指令存储器单元包括可操作以存储程序指令的第一存储器结构，以及可操作以存储从第一存储器结构提取的程序指令的第二存储器结构，以及发出用于执行的存储的程序指令。 如果前向分支指令的分辨率与其最后一个分辨率相同，则第二存储器结构可操作以识别前向程序重定向构造的重复发出，并且发出已经存储在第二存储器结构中的下一个程序指令。 第二存储器结构进一步可操作以发出反向程序重定向结构，确定目标指令是否存储在第二存储器结构中，如果目标指令存储在第二存储器结构中，则发出目标指令，并从 如果目标指令未被存储在第二存储器结构中的第一存储器结构。

公开(公告)号：WO2006110886A2

公开(公告)日：2006-10-19

申请号：PCT/US2006/013948

申请日：2006-04-11

Applicant: QUALCOMM Incorporated ,  AHMED, Muhammad ,  CODRESCU, Lucian ,  PLONDKE, Erich ,  ANDERSON, William C. ,  LESTER, Robert Allan ,  JONES, Phillip M.

Inventor： AHMED, Muhammad ,  CODRESCU, Lucian ,  PLONDKE, Erich ,  ANDERSON, William C. ,  LESTER, Robert Allan ,  JONES, Phillip M.

CPC classification number: G06F9/325 ,  G06F9/3802 ,  G06F9/3804 ,  G06F9/381

Abstract: An instruction memory unit comprises a first memory structure operable to store program instructions, and a second memory structure operable to store program instructions fetched from the first memory structure, and to issue stored program instructions for execution. The second memory structure is operable to identify a repeated issuance of a forward program redirect construct, and issue a next program instruction already stored in the second memory structure if a resolution of the forward branching instruction is identical to a last resolution of the same. The second memory structure is further operable to issue a backward program redirect construct, determine whether a target instruction is stored in the second memory structure, issue the target instruction if the target instruction is stored in the second memory structure, and fetch the target instruction from the first memory structure if the target instruction is not stored in the second memory structure.

Abstract translation: 指令存储单元包括可操作以存储程序指令的第一存储器结构，以及可操作以存储从第一存储器结构提取的程序指令并且发出用于执行的存储的程序指令的第二存储器结构。 如果前向分支指令的分辨率与其最后一个分辨率相同，则第二存储器结构可操作以识别正向程序重定向构造的重复发出，并发出已经存储在第二存储器结构中的下一个程序指令。 第二存储器结构还可操作以发出反向程序重定向结构，确定目标指令是否存储在第二存储器结构中，如果目标指令存储在第二存储器结构中，则发出目标指令，并从 如果目标指令没有存储在第二存储器结构中的第一存储器结构。

公开(公告)号：WO2010017043A9

公开(公告)日：2010-02-11

申请号：PCT/US2009/051705

申请日：2009-07-24

Applicant: QUALCOMM INCORPORATED ,  SHEN, Jian ,  LESTER, Robert, Allan

Inventor： SHEN, Jian ,  LESTER, Robert, Allan

IPC: G06F9/312 ,  G06F11/34

Abstract: A buffer management structure for processing systems is described. In one embodiment, the buffer management structure includes a storage module and a control module. The storage module includes a read position and can store a bit indicating a valid state of a transaction request in a write entry. The control module can receive an invalidation request and modify the bit to indicate an invalid state for the transaction request and discard the transaction request when the transaction request is in the read position.

公开(公告)号：WO2010017043A1

公开(公告)日：2010-02-11

申请号：PCT/US2009051705

申请日：2009-07-24

Applicant: QUALCOMM INC ,  SHEN JIAN ,  LESTER ROBERT ALLAN

Inventor： SHEN JIAN ,  LESTER ROBERT ALLAN

IPC: G06F9/312 ,  G06F11/34

CPC classification number: G06F12/1027 ,  Y02D10/13

Abstract: A buffer management structure for processing systems is described. In one embodiment, the buffer management structure includes a storage module and a control module. The storage module includes a read position and can store a bit indicating a valid state of a transaction request in a write entry. The control module can receive an invalidation request and modify the bit to indicate an invalid state for the transaction request and discard the transaction request when the transaction request is in the read position.

Abstract translation: 描述了用于处理系统的缓冲区管理结构。 在一个实施例中，缓冲管理结构包括存储模块和控制模块。 存储模块包括读取位置并且可以在写入条目中存储指示事务请求的有效状态的位。 控制模块可以接收无效请求并修改该位以指示交易请求的无效状态，并且当交易请求处于读取位置时丢弃交易请求。